In a semiconductor device 100, at least one of a first transistor and a second transistor that supply a second voltage in a step-down circuit stepping down a first voltage to the second voltage and outputting the second voltage from an output portion is configured such that the number of second contacts of a source electrode which is connected to a ground voltage or is supplied with the first voltage is larger than the number of first contacts connecting a diffusion layer and a first metal layer of a drain electrode connected to the output portion, and the number of second vias of the source electrode connected to the ground voltage or supplied with the first voltage is larger than the number of first vias connecting the first metal layer and a second metal layer of the drain electrode connected to the output portion.

A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

A semiconductor device includes a substrate, a lower electrode provided over the substrate, a capacitive insulating film, and an upper electrode provided over the lower electrode, wherein the lower electrode has an upper portion and a lower portion, and at a boundary between the upper portion and the lower portion, the diameter of the upper portion is smaller than the diameter of the lower portion.

Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

A semiconductor component for a memory device is provided. The semiconductor component comprises a first active region extending in a first direction; a second active region extending in the first direction; a first conductive layer disposed across the first active region and the second active region, in a second direction substantially perpendicular to the first direction; a second conductive layer extending in the first direction; and a first conductive via connecting the first conductive layer and the second conductive layer.

A method for forming a semiconductor memory structure includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; filling the contact opening with a conductive material to form a contact; forming a bit line directly above the contact and the pair of spacers, and forming a dielectric liner on sidewalls of the bit line. The pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction. The bit line extends in a second direction. The first direction is perpendicular to the second direction.