Provided is a memory device including a delay circuit having gate insulation films with thicknesses different from each other. The memory device includes a delay circuit configured to input an input signal and output an output signal, and circuit blocks configured to control an operation of reading or writing memory cell data in response to the input signal or the output signal. One of transistors constituting a circuit block has a gate insulation film having such a thickness that an effect of negative biased temperature instability (NBTI) or positive biased temperature instability (PBTI) on the transistors is minimized. The delay circuit may be affected little by a shift in a threshold voltage that may be caused by NTBI or PBTI, and thus, achieve target delay time.

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

A method and apparatus of a device that determines a cause and effect of congestion in this device is described. In an exemplary embodiment, the device measures a queue group occupancy of a queue group for a port in the device, where the queue group stores a plurality of packets to be communicated through that port. In addition, the device determines if the measurement indicates a potential congestion of the queue group, where the congestion prevents a packet from being communicated within a time period. If potential congestion exists on that queue group, the device further gathers information regarding packets to be transmitted through that port. For example, the device can gather statistics packets that are stored in the queue group and/or new enqueue packets.

Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer, a first work function layer, a barrier layer, and a second work function layer. The gate dielectric layer is formed on the sidewalls and the bottom surface of a trench. The work function layer is formed in the trench and contacts the sidewalls and the bottom surface of the gate dielectric layer. The barrier layer is formed on the top surface of the first work function layer. The second work function layer is formed on the barrier layer, and the sidewall of the second work function layer is separated from the gate dielectric layer by a distance. The semiconductor structure further includes an insulating layer in the trench and on the second work function layer.

A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.