A semiconductor device of the disclosure includes a substrate, a capacitor contact structure electrically connected to the substrate, a lower electrode connected to the capacitor contact structure, a capacitor insulating layer covering the lower electrode, and an upper electrode covering the capacitor insulating layer. The upper electrode includes a multiple layer on the capacitor insulating layer, and a cover layer on the multiple layer. The multiple layer includes a first electrode layer, a second electrode layer, and a first metal silicide layer between the first and second electrode layers. A work function of the first metal silicide layer is greater than a work function of the first electrode layer and a work function of the second electrode layer.

The present application discloses method for fabricating a conductive feature and a method for fabricating a semiconductor device. The method includes providing a substrate; forming a recess in the substrate; conformally forming a first nucleation layer in the recess; performing a post-treatment to the first nucleation layer; and forming a first bulk layer on the first nucleation layer to fill the recess. The first nucleation layer and the first bulk layer configure the conductive feature. The first nucleation layer and the first bulk layer include tungsten. The post-treatment includes a borane-containing reducing agent.

Disclosed herein is an apparatus that includes: a memory cell array including a plurality of first memory cell mats arranged in a first direction; a first voltage line supplied with a first voltage, the first voltage line extending in the first direction and being connected to a plurality of first vias each arranged over a corresponding one of even numbered ones of the plurality of first memory cell mats; and a second voltage line supplied with a second voltage different from the first voltage, the second voltage line extending in the first direction and being connected to a plurality of second vias each arranged over a corresponding one of odd numbered ones of the plurality of first memory cell mats.

Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a substrate provided with first trenches and including an active pillar positioned between adjacent two of the first trenches; forming, in the active pillar, a second trench whose bottom is greater than or equal to a bottom of the first trench in height; forming a first dielectric layer and a protective layer in the first trench, the first dielectric layer being positioned between the protective layer and the active pillar, and an upper surface of the first dielectric layer being lower than an upper surface of the active pillar; forming second dielectric layers on an exposed side wall of the first trench and a side wall of the second trench, a third trench being formed between each of the second dielectric layers and the protective layer, and a fourth trench being formed between the second dielectric layers.

A method for forming a semiconductor structure forming a blocking structure in the periphery region over the bottom layer. The method includes covering the middle layer over the bottom layer and the blocking structure. The method includes forming a patterned photoresist layer over the middle layer. The patterned photoresist layer is in the array region and directly over the blocking structure in the periphery region. The method includes transferring the pattern of the patterned photoresist layer to the bottom layer. The pattern of the patterned photoresist layer directly over the blocking structure is not formed in the bottom layer. The first portion of the substrate is in the array region and is an active area array. The second portion of the substrate is in the periphery region and is a guard ring. The third portion of the substrate is in the periphery region and is a periphery structure.

A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

A semiconductor memory device includes a substrate including memory cell, peripheral, and intermediate regions; a device isolation pattern; a partitioning pattern; bit lines extending in a first direction to a boundary between the intermediate and peripheral regions; storage node contacts on the memory cell region and filling a lower portion of a space between bit lines; landing pads on the storage node contacts; dummy storage node contacts on the intermediate region and filling a lower portion of a space between bit lines; dummy landing pads on the dummy storage node contacts; and a dam structure on the intermediate region, extending in the first direction, and having a bar shape, wherein the dummy landing pads are spaced apart from an edge of the dam structure in a second direction, and the dummy storage node contacts are in contact with the partitioning pattern.

A semiconductor device includes a substrate including a plurality of active patterns and a bit line intersecting at least one of the plurality of active patterns on the substrate and extending in a first direction. The bit line includes a first conductive pattern extending in the first direction, a bit line capping pattern extending in the first direction on the first conductive pattern, and a graphene pattern extending in the first direction between the first conductive pattern and the bit line capping pattern. The first conductive pattern may include ruthenium (Ru). The semiconductor device may also include one or more bit line contacts arranged in the first direction under the bit line, the one or more bit line contacts electrically connected to a respective one of the plurality of active patterns.

The present application provides a method of manufacturing a. memory device having a word line (WL) with improved adhesion between a work function member and a conductive layer. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation structure surrounding the active area; forming a recess extending into the semiconductor substrate and across the active area; forming a first insulating layer conformal to the recess; disposing a first conductive material conformal to the first insulating layer; forming a conductive member surrounded by the first conductive material; disposing a second conductive material over the conductive member and removing a portion of the first conductive material above the second conductive material to form a conductive layer enclosing the conductive member; and forming a second insulating layer over the conductive layer and conformal to the first insulating layer.

The present disclosure discloses a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method includes: providing a base, active regions arranged at intervals along a first direction being arranged in the base; forming, on the base, bit line structures arranged at intervals; forming a contact structure between two adjacent ones of the bit line structures; forming a barrier structure on the contact structure, the barrier structures being arranged in correspondence with and connected to the bit line structure, and a first recess being formed between any adjacent barrier structures; and forming a conductive structure in the first recess, the conductive structure including a protective layer and a conductive portion, and the protective layer wrapping a sidewall and a bottom wall of the conductive portion.