The present disclosure provides a method for manufacturing a fully self-aligned high-density 3D multi-layer memory, which relates to the technical field of memory manufacturing. The method includes the following steps: 1) forming a base structure; 2) grooving the base structure; 3) filling an insulating medium in the division groove; 4) deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, where the insulating medium is present between adjacent memory cell holes, and conductive medium layers and insulating medium layers of the base structure are exposed in the memory cell holes; and 5) disposing various layers of medium required by a preset memory structure layer by layer onto the inner walls of the memory cell holes. The semiconductor memory manufactured according to the present disclosure has high storage density.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

A memory circuit includes first and second read-only memory (ROM) cells aligned along a first active structure including a first shared source portion of the first and second ROM cells, third and fourth ROM cells aligned along a second active structure including a second shared source portion of the third and fourth ROM cells, a first bit line overlying the first and second ROM cells, a second bit line overlying the third and fourth ROM cells, and a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines. A conductive structure is electrically connected to each of the first and second shared source portions and the reference voltage line and is positioned in a metal layer below the same metal layer.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.