A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.

A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.

A method for making a semiconductor memory device comprising a plurality of memory cells for storing one or more data values, the method comprising: exposing a pattern on a wafer for creating structures for a plurality of memory cells for the semiconductor memory device, wherein the pattern is exposed by means of one or more charged particle beams; and varying an exposure dose of the one or more charged particle beams during exposure of the pattern to generate a set of one or more non-common features in one or more structures of at least one of the memory cells, so that the structures of the at least one memory cell differ from the corresponding structures of other memory cells of the semiconductor memory device.

Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P and NSi beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.