The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines and an insulating layer that is provided between the first bit lines and in a groove. First faces of the first bit lines are aligned on a first line and second faces of the first bit lines are aligned on a second line. A first face of the insulating layer is disposed at a third line that is a first distance from the first line in a first direction and a second face of the insulating layer is disposed at a fourth line that is a second distance from the second line in a second direction.

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

A semiconductor device is provided in which the power consumption can be reduced by reducing the driving voltage and the on-state current can be increased in a period in which a transistor having an extremely low off-state current is brought into an electrically floating state. The semiconductor device comprises a memory cell, a first circuit, and a second circuit. The memory cell includes a first transistor. The first transistor includes a first semiconductor layer, a first gate electrode, and a first back gate electrode. The first gate electrode is connected to a word line. The first back gate electrode is connected to a back gate line. The first circuit supplies a signal for controlling the conduction state of the first transistor to the word line. The second circuit supplies a voltage for controlling the threshold voltage of the first transistor to the back gate line. The second circuit has a function of bringing the back gate line into an electrically floating state in a period in which a signal for controlling the conduction state of the first transistor is supplied to the word line.

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer. Electrical resistance across first conductive layer between first and second end portions of first conductive layer is measured.

A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.