Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device, as well as a method for forming the IC. In some embodiments, the IC comprises a memory cell structure including a pair of control gates respectively separated from a substrate by a pair of floating gates and a pair of select gate electrodes disposed on opposite sides of the pair of control gates. A memory test structure includes a pair of dummy control gates respectively separated from the substrate by a pair of dummy floating gates and a pair of dummy select gate electrodes disposed on opposite sides of the pair of dummy control gates. The memory test structure further includes a pair of conductive floating gate test contact vias respectively extending through the pair of dummy control gates and reaching on the dummy floating gates.

3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.

Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.

A method for forming a staircase structure of a memory device includes the following operations. A first number of divisions are formed at different depths along a first direction in a stack structure and a trench structure between adjacent divisions, the stack structure comprising interleaved sacrificial material layers and dielectric material layers. A plurality of stairs are formed along a second direction. Each of the plurality of stairs includes the first number of divisions, and each of the divisions includes a first number of sacrificial portions. The second direction is perpendicular to the first direction. An insulating portion is formed in the trench structure. A top sacrificial portion is formed on a top surface of each of the first number of divisions and in contact with the insulating portion. The top sacrificial portion is replaced with a conductor portion through a slit structure in the insulating portion and in contact with the top sacrificial portion.

A semiconductor device includes a cell array including a source structure, a peripheral circuit, an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit, and a decoupling structure configured to prevent a coupling capacitor that occurs between the cell array and the interconnection structure.

Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.

A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The invention also provides a manufacturing method for manufacturing the above-mentioned split gate flash memory cell, and the manufacturing method provided by the invention can be compatible with the existing manufacturing process of the split gate flash memory cell without increasing the process cost and the process complexity. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.

A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.