The present application discloses a method for manufacturing a semiconductor device, which includes the following steps: step 1: forming first gate structures on a semiconductor substrate; step 2: performing a first etching process to etch the semiconductor substrate on at least one side of each first gate structure to a certain depth and form a first groove; step 3: performing a stress memorization process, including step 31: forming a stress dielectric layer, the stress dielectric layer covering a peripheral surface of each first gate structure and being filled in the first groove; step 32: performing annealing to transfer the stress of the stress dielectric layer to a channel region; step 33: removing the stress dielectric layer. The present application can increase the effect of transferring the stress of the stress dielectric layer to the channel region, thereby increasing the mobility of channel carriers.

A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions. Some embodiments include methods of forming integrated assemblies.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

A method of manufacturing a memory structure including the following steps is provided. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification treatment includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures.

A floating gate fabrication method is disclosed. The method includes: providing a substrate, and depositing an oxide layer on the substrate; fabricating a shallow trench isolation in the substrate, a top surface of the shallow trench isolation being higher than a top surface of the oxide layer; depositing a polysilicon layer on the oxide layer and the shallow trench isolation; performing a first thermal annealing process on the polysilicon layer, thereby repairing cavities formed after the deposition of the polysilicon layer; implanting ions into the polysilicon layer; performing a second thermal annealing process on the polysilicon layer, thereby activating the implanted ions and repairing again the cavities formed after the deposition of the polysilicon layer; and planarizing the polysilicon layer to form a floating gate.