A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Provided are a dielectric material including a compound represented by Formula 1, a device including the same, and a method of preparing the dielectric material:
(1−x)K.sub.aNa.sub.bNbO.sub.3.xM(A.sub.cSb.sub.d)O.sub.3  [Formula 1] wherein, in Formula 1, M is a Group 2 element, A is a trivalent element, and 0<x<1, 0<a<1, 0<b<1, 0<c<1, 0<d<1, a+b=1, and c+d=1.

Provided are a dielectric material including a compound represented by Formula 1, a device including the same, and a method of preparing the dielectric material:
(1−x)K.sub.aNa.sub.bNbO.sub.3.xM(A.sub.cSb.sub.d)O.sub.3  [Formula 1] wherein, in Formula 1, M is a Group 2 element, A is a trivalent element, and 0<x<1, 0<a<1, 0<b<1, 0<c<1, 0<d<1, a+b=1, and c+d=1.

A thin film structure includes a first conductive layer, a dielectric material layer on the first conductive layer, and an upper layer on the dielectric material layer. The dielectric material layer including Hf.sub.xA.sub.1-xO.sub.2 satisfies at least one of a first condition and a second condition. In the first condition the dielectric material layer is formed to a thickness of 5 nm or less and in the second condition the x in Hf.sub.xA.sub.1-xO.sub.2 is in a range of 0.3 to 0.5.

A thin film structure includes a first conductive layer, a dielectric material layer on the first conductive layer, and an upper layer on the dielectric material layer. The dielectric material layer including Hf.sub.xA.sub.1-xO.sub.2 satisfies at least one of a first condition and a second condition. In the first condition the dielectric material layer is formed to a thickness of 5 nm or less and in the second condition the x in Hf.sub.xA.sub.1-xO.sub.2 is in a range of 0.3 to 0.5.

A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.

Provided are a dielectric material including a compound represented by Formula 1, a device including the same, and a method of preparing the dielectric material:

(1−x)K.sub.aNa.sub.bNbO.sub.3.xM(A.sub.cSb.sub.d)O.sub.3  [Formula 1] wherein, in Formula 1, M is a Group 2 element, A is a trivalent element, and 0<x<1, 0<a<1, 0<b<1, 0<c<1, 0<d<1, a+b=1, and c+d=1.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.