A method of manufacturing a memory device includes sequentially forming a first magnetization layer, a tunnel barrier layer, and a second magnetization layer on each other; forming a magnetic tunnel junction structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; forming a sidewall metal layer by etching a portion of a redeposited metal covering a sidewall of the magnetic tunnel junction structure; performing an oxidizing operation that includes oxidizing an exposed surface of the sidewall metal layer to provide an oxidized sidewall metal layer; and performing an irradiating operation that includes irradiating an ion beam towards the oxidized sidewall metal layer. A sidewall insulating layer covering a sidewall of the magnetic tunnel junction structure is formed by alternately performing the oxidizing operation and the irradiating operation two or more times.

A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

A metallic hardmask is formed having a selected stress designed to create a selected amount of positive wafer bow. In preferred embodiments, metallic hardmask is disposed on a memory pillar layer over a wafer substrate. A set of memory pillars using the metal hardmask. Because of the positive wafer bow, the patterned set of memory pillars at both the edges and the central portion of the wafer substrate are aligned with a respective contact for a memory device. A positive wafer bow is defined as a bowed wafer substrate where a central portion of a patterned side of the wafer substrate is lower than edges of the wafer substrate.

A metallic hardmask is formed having a selected stress designed to create a selected amount of positive wafer bow. In preferred embodiments, metallic hardmask is disposed on a memory pillar layer over a wafer substrate. A set of memory pillars using the metal hardmask. Because of the positive wafer bow, the patterned set of memory pillars at both the edges and the central portion of the wafer substrate are aligned with a respective contact for a memory device. A positive wafer bow is defined as a bowed wafer substrate where a central portion of a patterned side of the wafer substrate is lower than edges of the wafer substrate.

A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.

A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H.sub.2, or a reducing species.

There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

An apparatus is provided which comprises: a stack comprising a magnetoelectric (ME such as BiFeO.sub.3, (LaBi)FeO.sub.3, LuFeO.sub.3, PMN-PT, PZT, AlN, SmBiFeO.sub.3, Cr.sub.2O.sub.3, etc.) material and a transition metal dichalcogenide (TMD such as MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2, PtS.sub.2, PtSe.sub.2, WTe.sub.2, MoTe.sub.2, graphene, etc.); a magnet adjacent to a first portion of the TMD of the stack; a first interconnect adjacent to the magnet; a second interconnect adjacent to the ME material of the stack; and a third interconnect adjacent to a second portion of the TMD of the stack.

The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.