The disclosed technology relates generally to semiconductor devices, and more particularly to a layer stack for a magnetic tunnel junction (MTJ) device, and a method of forming the same. According to an aspect, a layer stack for a (MTJ) device comprises a seed layer structure, a pinning layer structure arranged above the seed layer structure, and above the pinning layer structure a Fe-comprising reference layer structure and a free layer structure separated by a tunnel barrier layer. The seed layer structure comprises a Ru-comprising layer and a Cr-comprising layer. The Cr-comprising layer forms an upper layer of the seed layer structure.

A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Ru) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

A magnetic memory device includes a conductive line extending in a first direction, a magnetic line extending in a second direction intersecting the first direction on the conductive line, the magnetic line intersecting the conductive line, and a magnetic pattern disposed between the conductive line and the magnetic line. The magnetic pattern has first sidewalls opposite to each other in the first direction, and second sidewalls opposite to each other in the second direction. The second sidewalls of the magnetic pattern are aligned with sidewalls of the conductive line, respectively.

A method of manufacturing and resultant device are directed to an inverted wide-base double magnetic tunnel junction device having both high-efficiency and high-retention arrays. The method includes a method of manufacturing, on a common stack, a high-efficiency array and a high-retention array for an inverted wide-base double magnetic tunnel junction device. The method comprises, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer. The first magnetic tunnel junction stack for the high-retention array has a high-retention critical dimension (CD) (HRCD) that is larger than a high-efficiency CD (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted for the high-retention array and is not shorted for the high-efficiency array.

An integrated circuit (IC) is provided that includes a plurality of physical unclonable function (PUF) structures located in a PUF area. Each PUF structure of the plurality of PUF structures includes at least a PUF top electrically conductive structure containing random sidewall voids and random line openings which can provide an encrypted security code to the IC. The IC further includes a plurality of memory structures located in a memory area that is located laterally adjacent to the PUF area. Each memory structure of the plurality of memory structures includes a memory element sandwiched between a bottom electrically conductive structure and a top electrically conductive structure. The top electrically conductive structures are devoid of sidewall voids and line openings.

A magnetic domain wall movement type magnetic recording element according to an embodiment includes: a first ferromagnetic layer which includes a ferromagnetic body; a non-magnetic layer which faces the first ferromagnetic layer; and a magnetic recording layer which faces a surface of the non-magnetic layer on a side opposite to the first ferromagnetic layer and extends in a first direction. A first surface of the magnetic recording layer which faces the non-magnetic layer has a smaller arithmetic mean roughness than a second surface opposite to the first surface.

This spin element includes: a current-carrying part that extends in a first direction; and an element part that is laminated on one surface of the current-carrying part, wherein the current-carrying part includes a first wiring and a second wiring in order from a side of the element part, and wherein both of the first wiring and the second wiring are metals and temperature dependence of resistivity of the first wiring is larger than temperature dependence of resistivity of the second wiring in at least a temperature range of −40° C. to 100° C.

An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type.

A sputtering apparatus including a chamber, a gas supply configured to supply the chamber with a first gas and a second inert gas, the first inert gas and the second inert gas having a first evaporation point and second evaporation point, respectively, a plurality of sputter guns in an upper portion of the chamber, a chuck in a lower portion of the chamber and facing the sputter guns, the chuck configured to accommodate a substrate thereon, and a cooling unit connected to a lower portion of the chuck, the cooling unit configured to cool the chuck to a temperature less than the first evaporation point and greater than the second evaporation point, and a method of fabricating a magnetic memory device may be provided.