A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

A storage layer of a magnetic tunnel junction (MTJ) element is disclosed. The storage layer having perpendicular magnetic anisotropy includes a first ferromagnetic layer, a first dust layer disposed directly on the first ferromagnetic layer, a second ferromagnetic layer disposed directly on the first dust layer, a second dust layer disposed directly on the second ferromagnetic layer, and a third ferromagnetic layer disposed directly on the second dust layer. A material of the first dust layer is different from a material of the second dust layer.

One illustrative MRAM cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the MTJ element includes a bottom insulation layer positioned above the bottom electrode, a top insulation layer positioned above the bottom electrode; and a first ferromagnetic material layer positioned between the bottom insulation layer and the top insulation layer.

At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

A spin element according to the present embodiment includes a wiring, a laminate including a first ferromagnetic layer laminated on the wiring, a first conductive part and a second conductive part with the first ferromagnetic layer therebetween in a plan view in a lamination direction, and an intermediate layer which is in contact with the wiring and is between the first conductive part and the wiring, wherein a diffusion coefficient of a second element including the intermediate layer with respect to a first element including the wiring is smaller than a diffusion coefficient of a third element constituting the first conductive part with respect to the first element or a diffusion coefficient of the third element including the first conductive part with respect to the second element constituting the wiring is smaller than a diffusion coefficient of the third element with respect to the first element constituting the intermediate layer.

A magnetic recording array includes a plurality of spin elements arranged in a matrix, each spin element including a wiring and a stacked body that includes a first ferromagnetic layer stacked on the wiring, a plurality of write wirings connected to first ends of the respective wirings in the plurality of spin elements, a plurality of read wirings connected to the respective stacked bodies in the plurality of spin elements, and a plurality of common wirings connected to second ends of the wirings in the respective spin elements belonging to the same row, wherein the common wiring has an electrical resistance lower than the electrical resistance of the write wiring or the read wiring.

The invention provides a semiconductor structure, the semiconductor structure includes a dielectric layer, a plurality of MTJ stacked elements and at least one dummy MTJ stacked element located in the dielectric layer, a first nitride layer covering at least the sidewalls of the MTJ stacked elements and the dummy MTJ stacked elements, a second nitride layer covering the top surfaces of the dummy MTJ stacked elements, the thickness of the second nitride layer is greater than the thickness of the first nitride layer, and a plurality of contact structures located in the dielectric layer and electrically connected with each MTJ stacked element.

Embodiments disclosed herein comprise package substrates and methods of forming such package substrates. In an embodiment, a package substrate comprises a core, where the core comprises glass. In an embodiment, an opening if formed through the core. In an embodiment, a magnetic region is disposed in the opening.

A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.

A semiconductor device including a second magnetic tunnel junction stack aligned above a spin conductor layer above a first magnetic junction stack, a sidewall dielectric surrounding the second magnetic tunnel junction stack, a vertical side surface of the sidewall dielectric is aligned with vertical side surfaces of the spin conductor layer and the first magnetic junction stack. A method including forming a first magnetic tunnel junction stack, a spin conductor layer and a second magnetic tunnel junction stack, patterning the second magnetic tunnel junction stack, while not patterning the spin conductor layer and the first magnetic tunnel junction stack, forming a sidewall dielectric and a polymer layer on the sidewall dielectric. A method including patterning a second magnetic tunnel junction stack, while not patterning a spin conductor layer below the second magnetic tunnel junction stack nor a first magnetic tunnel junction stack below the spin conductor layer.