A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.

A magnetic memory device may include a perpendicular magnetic structure, an in-plane magnetic structure, a free magnetic pattern between the perpendicular magnetic structure and the in-plane magnetic structure, and a tunnel barrier pattern between the perpendicular magnetic structure and the free magnetic pattern. The perpendicular magnetic structure may include at least one pinned pattern which has a perpendicular magnetization direction that is pinned to a specific direction, and the free magnetic pattern may have a switchable perpendicular magnetization direction. The in-plane magnetic structure may include a first magnetic pattern and a second magnetic pattern, and each of the first and second magnetic patterns may have a different respective in-plane magnetization direction.

A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.

A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

A magnetoresistive device includes a spin-orbit-torque (SOT) electrode layer, and a first magnetic layer, a first non-magnetic layer, and a second magnetic layer sequentially stacked over the SOT electrode layer. An interface layer is located between the SOT electrode layer and the first magnetic layer, and an etch stop layer covers a surface portion of the SOT electrode layer and is located adjacent the interface layer. The interface layer includes a metal having a spin diffusion length that is greater than a thickness of the interface layer, and the etch stop layer includes an oxide or nitride material of the metal.

A magnetic element according to an embodiment includes a wiring layer extending in a first direction and including a ferromagnetic material and a nonmagnetic layer laminated on the wiring layer in a second direction. The wiring layer includes a side surface inclined with respect to the second direction in a cross section orthogonal to the first direction. The side surface has one or more bending points at which an inclination angle with respect to the second direction becomes discontinuous. An inclination angle of a first inclined surface far from the nonmagnetic layer is smaller than an inclination angle of a second inclined surface close to the nonmagnetic layer in a state in which a first bending point at a position farthest from the nonmagnetic layer among the bending points is interposed between the inclination angles.

A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

A method includes forming a magnetic tunnel junction (MTJ) stack over a substrate. The MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer. The method also includes patterning the top magnetic layer in a first etch process, after the patterning of the top magnetic layer depositing a spacer on sidewalls of the patterned top magnetic layer, and patterning the bottom magnetic layer in a second etch process.