Insulated phase change memory devices are provided that include a first electrode; a second electrode; a phase change material disposed in an electrical path between the first electrode and the second electrode; and a porous dielectric configured to concentrate heat produced by a reset current carried through the phase change material between the first electrode and the second electrode to mitigate an amount of heat that escapes from the phase change material. The porous dielectric may be an inherently porous dielectric material or a dielectric material in which porous structures are induced during fabrication. Methods of fabrication of such devices are also provided.

Methods for manufacturing memory resistor devices and memory resistor devices manufactured according to such methods. A method includes depositing a first layer of dielectric material onto a substrate comprising a first electrode; bombarding the deposited first layer with an ion beam to create one or more defects in the first layer; depositing a second electrode such that the deposited first layer is between the first electrode and the second electrode; electroforming the first layer by applying an electroforming voltage between the first electrode and the second electrode.

A superlattice phase-change thin film with a low density change, a phase-change memory and a preparation method. The superlattice phase-change thin film includes first phase-change layers (7) and second phase-change layers (8) that are alternately stacked to form a periodic structure; during crystallization, the first phase-change layer (7) has a conventional positive density change, and the second phase-change layer (8) has an abnormal negative density change, therefore, the abnormal density reduction and volume increase of the second phase-change layer (8) during crystallization can be used to offset the volume reduction of the first phase-change layer (7) during crystallization.

The present disclosure provides a semiconductor chip including a functional area, a first end, a second end, a third end, and a connecting portion. The functional area has first and second sides opposite to each other. The first end is disposed on the first side and the third end is disposed on the first side, wherein the semiconductor chip is switched on or off according to the drive signal received between the third end and the first end, and the connecting portion is disposed on the first side of the functional area and connected to the first end and the third end, wherein when the temperature rises above the a first temperature, the connecting portion is in a conductive state, and when the temperature drops to be not higher than a third temperature, the connecting portion is in an insulated state.

A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.

Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.

A resistive switching memory stack, comprised of a bottom electrode, an oxide layer located on the bottom electrode; and a top electrode located on the oxide layer. The top electrode is comprised of a first layer, an intermediate layer located directly on the first layer, and a top layer located on top of the intermediate layer. Wherein the intermediate layer is comprised of a doped carbide active layer.

A non-volatile memory cell includes a thin film resistor (TFR) in series and between a top state influencing electrode and a top wire. The TFR limits or generally reduces the electrical current at the top state influencing electrode from the top wire. As such, non-volatile memory cell endurance may be improved and adverse impacts to component(s) that neighbor the non-volatile memory cell may be limited. The TFR is additionally utilized as an etch stop when forming a top wire trench associated with the fabrication of the top wire. In some non-volatile memory cells where cell symmetry is desired, an additional TFR may be formed between a bottom wire and a bottom state influencing electrode.

A semiconductor device is provided. The semiconductor device includes a substrate a substrate, a first electrode structure on the substrate, the first electrode structure including first insulating patterns and first electrode patterns, the first insulating patterns alternately stacked with the first electrode patterns, a second electrode pattern on a sidewall of the first electrode structure, and a data storage film on a sidewall of the second electrode pattern. The data storage film has a variable resistance.