A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.

An resistive random-access memory (RRAM) device including an first crystalline semiconductor layer disposed adjacent to a crystalline semiconductor substrate, a crystal lattice edge-dislocation segment disposed at an interface of the first crystalline semiconductor layer and crystalline semiconductor substrate, the lattice edge-dislocation segment including first and second segment ends, a first ion-source electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the first segment end of the lattice edge-dislocation segment, and a second electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the second segment end of the lattice edge-dislocation segment.

A selector includes a first electrode, a second electrode, and a selector layer provided between the first electrode and the second electrode and contains Si.sub.xTe.sub.yN.sub.z. The x, y, and z of the Si.sub.xTe.sub.yN.sub.z satisfy 0<x≤35, 15≤y≤50, and 50<z≤85, satisfy 0<x≤45, 15≤y≤55, and 40<z≤85, or satisfy 0<x≤55, 15≤y≤65, and 30<z≤85.

A semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked with each other, and a channel layer passing through the stacked structure, wherein the channel layer is a single layer, the single layer including a first GIDL region, a cell region, and a second GIDL region, and the first GIDL region has a greater thickness than each of the cell region and the second GIDL region.

A memory device includes a transistor, a memory cell, and an interconnect layer. The transistor includes a bottom source/drain portion, a channel portion, and a top source/drain portion stacked from bottom to top and a gate structure surrounding the channel portion. The memory cell includes a nanowire bottom electrode, a first dielectric layer, a second dielectric layer, and a top electrode. The first dielectric layer laterally surrounds the nanowire bottom electrode. The second dielectric layer is over the nanowire bottom electrode and the first dielectric layer. The second dielectric layer is in contact with a top surface of the nanowire bottom electrode and a sidewall of the first dielectric layer. The top electrode covers the second dielectric layer. The interconnect layer is over the transistor and the memory cell to interconnect the transistor and the memory cell.

A method for manufacturing a high-density three-dimensional programmable memory, relating to the memory manufacturing technology, comprises the following steps: 1) forming a base structure; 2) grooving the base structure; 3) disposing, storage medium layers required by a preset memory structure layer by layer on an inner wall of the division groove; 4) filling a core medium in the division groove to form a core medium layer; 5) etching, through a mask etching process, to form deep holes along the separation division groove filled with the core where the deep holes truncate the core medium in the division groove; and 6) filling an insulation medium in the deep holes. The method has the beneficial effects of low costs and the highest storage density.

A phase-change memory device includes a bottom electrode; a stack of alternating electrical conductor layers directly contacting a top surface of the bottom electrode; a metal pillar directly contacting a top surface of the stack; a phase change material element directly contacting a top surface of the metal pillar; and a top electrode on the phase change material element, wherein a lateral dimension of the metal pillar is smaller than that of the stack.

A phase-change memory device includes a bottom electrode; a stack of alternating electrical conductor layers directly contacting a top surface of the bottom electrode; a metal pillar directly contacting a top surface of the stack; a phase change material element directly contacting a top surface of the metal pillar; and a top electrode on the phase change material element, wherein a lateral dimension of the metal pillar is smaller than that of the stack.

A variable resistance memory device includes: a supporting layer including an insulating material; a variable resistance layer on the supporting layer and including a first layer including a metal oxide and metal nanoparticles, the variable resistance layer including a second layer on the first layer and including an oxide; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a gate electrode on the gate insulating layer. The metal nanoparticles in the variable resistance layer include a first metal capable of combining with oxygen ions of the metal oxide, thereby increasing oxygen vacancies.

A hybrid switch and memory cell includes a transistor device that has an atomically-thin semiconductor material channel, source/drain electrodes, and gate dielectric. The cell includes a resistive-random-access-memory having a thin conductive edge and a 2D insulator layer over the thin conductive edge, wherein the 2D insulator layer extends over the semiconductor channel and serves as the gate dielectric in the transistor device.