A vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and respective insulation layers. The gate patterns may be stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns may extend in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate. The gate patterns may include pads, respectively, at edge portions thereof in the first direction. The respective insulation layers may be between adjacent gate patterns in the vertical direction. The gate patterns and the insulation layer on the pad region may serve as a pad structure, and the pad structure may include a first staircase structure having a stepped shape, a second staircase structure having a stepped shape and disposed below the first staircase structure, a flat surface portion between the first and second staircase structures, and a dummy staircase structure formed on the flat surface portion. The dummy staircase structure may be spaced apart from each of the first and second staircase structures.

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure comprises: forming an interconnect layer and a conductive layer covered on a surface of the interconnect layer; forming a protective layer covering a surface of the conductive layer away from the interconnect layer; forming a trench penetrating the protective layer and the conductive layer; and filling a dielectric layer in the trench, and forming an air gap in the dielectric layer, the air gap extending from the trench in the conductive layer into the trench in the protective layer.

Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

A transistor device includes a transistor and programmable controller. The controller has an output that controls operation of the transistor. The controller includes analog computing circuitry and optionally digital computing circuitry that may be used to setup the analog computing circuitry. In addition to two connectors for connecting the transistor into an external circuit, the device includes a further connector that provides an input to the controller and through which the control can be programmed post manufacture. The transistor device may be a discrete component in which transistor and controlling circuitry are held in packaging, the three connectors exposed through the packaging in order to connect the device to an external circuit.

A transistor device includes a transistor and programmable controller. The controller has an output that controls operation of the transistor. The controller includes analog computing circuitry and optionally digital computing circuitry that may be used to setup the analog computing circuitry. In addition to two connectors for connecting the transistor into an external circuit, the device includes a further connector that provides an input to the controller and through which the control can be programmed post manufacture. The transistor device may be a discrete component in which transistor and controlling circuitry are held in packaging, the three connectors exposed through the packaging in order to connect the device to an external circuit.

The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

A method for method for manufacturing a rutile titanium dioxide layer according to the inventive concept includes forming a sacrificial layer on a substrate, and depositing a titanium dioxide (TiO.sub.2) material on the sacrificial layer. The sacrificial layer includes a metal oxide of a rutile phase. An amount of oxygen vacancy of the sacrificial layer after depositing the titanium dioxide material is greater than an amount of oxygen vacancy of the sacrificial layer before depositing the titanium dioxide material. The metal oxide includes a metal different from titanium (Ti).

A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.

A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.