A semiconductor device includes; a first transistor on a substrate and including a first gate electrode, a second transistor on the substrate and including a second gate electrode adjacent to the first gate electrode, an electrode structure including electrodes vertically stacked on the first and second transistors and including first and second pads adjacent to in the first direction, first and second landing pads between the substrate and the electrode structure connected respectively to the first and second landing pads, a first penetration electrode penetrating the electrode structure to connect the first landing pad and the first pad, a second penetration electrode penetrating the electrode structure to connect the second landing pad and the second pad, and lower interconnection lines between the first landing pad and the second landing pad and extending in a second direction substantially perpendicular to the first direction.

A semiconductor device includes a first substrate structure including a substrate, circuit devices, and first bonding metal layers on the circuit devices, and a second substrate structure connected to the first substrate structure on the first substrate structure, wherein the second substrate structure includes a plate layer having a first region and a second region, gate electrodes stacked below the plate layer and extending by different lengths in a second direction in the second region, channel structures penetrating the gate electrodes and each including a channel layer, in the first region, input/output contact structures penetrating the plate layer and the gate electrodes and each including a contact conductive layer, in the second region, and second bonding metal layers connected to the first bonding metal layers, wherein a level of upper surfaces of the input/output contact structures is higher than a level of upper surfaces of the channel structures.

A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, and vertical channel structures provided in vertical channel holes penetrating the stack structure. Each of the vertical channel structures may include a data storage pattern covering an inner side surface of each of the vertical channel holes, a vertical semiconductor pattern covering the data storage pattern, and a gapfill insulating pattern filling an internal space enclosed by the vertical semiconductor pattern. The vertical semiconductor pattern may have a first surface which is in contact with the gapfill insulating pattern, and a second surface which is in contact with the data storage pattern. A germanium concentration in the vertical semiconductor pattern may decrease in a direction from the first surface toward the second surface.

Provided is a semiconductor package including a redistribution structure including at least one redistribution insulating layer and at least one redistribution pattern, at least one semiconductor chip located on the redistribution structure, and a molding layer located on the redistribution structure and covering the at least one semiconductor chip. The redistribution pattern includes a redistribution via passing through the redistribution insulating layer and extending in a first direction perpendicular to a top surface of the redistribution structure, and a redistribution line extending in a second direction parallel to the top surface of the redistribution structure. Inner side walls of the redistribution via have a certain inclination, and a difference between a thickness of a central portion of the redistribution line and a thickness of an edge of the redistribution line ranges from 1% to 10% of the thickness of the central portion of the redistribution line.

Provided is a semiconductor package including a redistribution structure including at least one redistribution insulating layer and at least one redistribution pattern, at least one semiconductor chip located on the redistribution structure, and a molding layer located on the redistribution structure and covering the at least one semiconductor chip. The redistribution pattern includes a redistribution via passing through the redistribution insulating layer and extending in a first direction perpendicular to a top surface of the redistribution structure, and a redistribution line extending in a second direction parallel to the top surface of the redistribution structure. Inner side walls of the redistribution via have a certain inclination, and a difference between a thickness of a central portion of the redistribution line and a thickness of an edge of the redistribution line ranges from 1% to 10% of the thickness of the central portion of the redistribution line.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus includes greater than eight pillars and less than three hundred pillars, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

A semiconductor device is provided. The semiconductor device includes a first substrate layer having a first side over which devices are formed. In the semiconductor device, a first dielectric structure is formed over the first side of the first substrate layer in which the devices are positioned. The first dielectric structure includes a bottom surface in contact with the first side of the first substrate layer. A portion of the bottom surface of the first dielectric structure is not covered by the first substrate layer. The semiconductor device also includes a first electronic structure positioned over the uncovered portion of the bottom surface of the first dielectric structure such that the first electronic structure and the first substrate layer are positioned at a same side of the bottom surface of the first dielectric structure. The first electronic structure is bonded to the first dielectric structure.