In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, a non-conductive layer aligned with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

A memory chip stack is described. The memory chip stack includes memory chips having a first plurality of memory channels, where non-yielding ones of the memory channels are to be disabled during operation of the memory chip stack. The first plurality of memory channels have a second plurality of memory banks, where non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack.

A memory chip stack is described. The memory chip stack includes memory chips having a first plurality of memory channels, where non-yielding ones of the memory channels are to be disabled during operation of the memory chip stack. The first plurality of memory channels have a second plurality of memory banks, where non-yielding ones of the memory banks within yielding ones of the memory channels are to be disabled during the operation of the memory chip stack.

A high bandwidth memory is provided. The high bandwidth memory includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.

A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.

A semiconductor device includes a first substrate and a plurality of electrode layers above the first substrate and separated from each other in a first direction. The device includes a plurality of plugs provided on upper surfaces or lower surfaces of the plurality of electrode layers and a plurality of columnar portions in the plurality of electrode layers and extending in the first direction. A charge storage layer is between a semiconductor layer of the columnar portions and the electrode layers. A second substrate is provided above the plurality of electrode layers. A plurality of first transistors is provided on an upper surface of the first substrate and are electrically connected to the plurality of plugs. A plurality of second transistors is provided on a lower surface of the second substrate and are electrically connected to the plurality of columnar portions.

The present disclosure relates to a three-dimensional (3D) memory and a fabrication method thereof. The method includes forming a memory chip on a first substrate, disposing a first semiconductor layer on the memory chip, forming a plurality of first contacts through the first semiconductor layer, forming a first peripheral circuit chip based on the first semiconductor layer, disposing a second semiconductor layer on the first peripheral circuit chip, forming a plurality of second contacts through the second semiconductor layer, and forming a second peripheral circuit chip based on the second semiconductor layer. The first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts, and the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

A radiation detection device includes a non-volatile memory chip including a plurality of stacked memory cells, and a controller configured to detect gamma rays incident on the non-volatile memory chip during a gamma ray detection window according to a data inversion or a threshold voltage change of at least some of the memory cells in the non-volatile memory chip during the gamma ray detection window.

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.