Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

A magnetic element according to an embodiment includes a wiring layer extending in a first direction and including a ferromagnetic material and a nonmagnetic layer laminated on the wiring layer in a second direction. The wiring layer includes a side surface inclined with respect to the second direction in a cross section orthogonal to the first direction. The side surface has one or more bending points at which an inclination angle with respect to the second direction becomes discontinuous. An inclination angle of a first inclined surface far from the nonmagnetic layer is smaller than an inclination angle of a second inclined surface close to the nonmagnetic layer in a state in which a first bending point at a position farthest from the nonmagnetic layer among the bending points is interposed between the inclination angles.

A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

A magnetoresistance effect element according to an embodiment includes: a spin orbit torque wiring extending in a first direction; a laminated body laminated on the spin orbit torque wiring and having a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer; a conductive layer in contact with a side of the laminated body opposite to the spin orbit torque wiring; and a heat dissipation layer separated from the laminated body in the first direction and connected to the spin orbit torque wiring and the conductive layer.

A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

A method of forming a memory device is provided. The method comprises: forming a first storage portion on a substrate; forming a conductive layer on the first storage portion, wherein the conductive layer has a first surface coupled to the first storage portion; and forming a second storage portion on a second surface of the conductive layer, wherein the second surface is opposite to the first surface.

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.

An etching method includes: preparing a workpiece including a metal multilayer film having a magnetic tunnel junction and a mask formed by an inorganic material on the metal multilayer film; and etching the metal multilayer film by plasma of a mixed gas of ethylene gas and oxygen gas using the mask.