A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

A tunnel magnetoresistance effect (TMR) device includes an exchange coupling film having a first ferromagnetic layer, which is at least a portion of a fixed magnetic layer, and an antiferromagnetic layer laminated on the first ferromagnetic layer. The ferromagnetic layer includes an X(Cr—Mn) layer containing one or two or more elements X selected from the group consisting of the platinum group elements and Ni, and also containing Mn and Cr. The X(Cr—Mn) layer has a first region relatively near the first ferromagnetic layer, and a second region relatively far away from the first ferromagnetic layer, and the content of Mn in the first region is higher than that in the second region.

According to one embodiment, a memory system classifies a plurality of nonvolatile memory dies connected to a plurality of channels, into a plurality of die groups such that each of the plurality of nonvolatile memory dies belongs to only one die group. The memory system performs a data write/read operation for one die group of the plurality of die groups in accordance with an I/O command from a host designating one of a plurality of regions including at least one region corresponding to each die group. The memory system manages a group of free blocks in the nonvolatile memory for each of the plurality of die group by using a plurality of free block pools corresponding to the plurality of die groups.

A magnetoresistive memory cell includes an MTJ element including a magnetization free layer and a pure spin injection source. The pure spin injection source includes a BiSb layer coupled to the magnetization free layer. By flowing an in-plane current through the BiSb layer, this arrangement is capable of providing magnetization reversal of the magnetization free layer.

A semiconductor package includes: a first semiconductor chip stack including a plurality of first semiconductor chips which are stacked in a vertical direction; a bridge die stack disposed to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge dies which are stacked in the vertical direction, wherein the bridge dies include through electrodes, respectively, and the through electrodes aligned in the vertical direction are connected to each other through a connection electrode between the bridge dies; a redistribution layer disposed over the first semiconductor chip stack and the bridge die stack; a second semiconductor chip disposed over the redistribution layer and configured to receive a voltage through the through electrodes aligned in the vertical direction, the connection electrode, and the redistribution layer; and a voltage regulator configured to adjust the voltage.

A variable-resistance nonvolatile memory element 11 of the present disclosure has a stack 30 including at least a magnetization fixed layer 31, an intermediate layer 32, and a storage layer 33, and a nonmagnetic material 36 is dispersed in at least one of the magnetization fixed layer 31 and the storage layer 33.

A high bandwidth memory is provided. The high bandwidth memory includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.