We disclose an array of Infra-Red (IR) detectors comprising at least one dielectric membrane formed on a semiconductor substrate comprising an etched portion; at least two IR detectors, and at least one patterned layer formed within or on one or both sides of the said dielectric membrane for controlling the IR absorption of at least one of the IR detectors. The patterned layer comprises laterally spaced structures.

A photothermal converter using a wavelength selective perfect absorber made of a low-loss metal material or dielectric and a heat detection sensor are combined to develop a sensor that efficiently converts light of a specific wavelength into heat and further electrically detects the heat. Here, since the wavelength selective perfect absorber of the present invention has a periodic structure, it has high directivity, and can also be used as a small motion sensor or a watching sensor using detection of thermal radiation. In addition, it can also be used as a high-precision small position sensor by being combined with a laser light source matching the resonance wavelength of the sensor.

A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.

In described examples, an integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

The present invention relates to a semiconductor device, including: a substrate; a plurality of first semiconductor elements and a second semiconductor element arranged on a mount area of the substrate; an external electrode to supply electricity to the first and second semiconductor elements; and a frame of reflective material formed at a periphery of the mount area. Extensions of the first external electrodes are formed at the inner side of the plurality of wirings, and the first external electrodes are formed along the periphery of the mount area at the outer side of at least one of the second external electrodes or the wiring connected to the second external electrodes, and electrodes of the plurality of first semiconductor elements are electrically connected to the pair of first external electrodes by a bonding wire that bridges across at least one of the pair of the second external electrodes or the wiring electrically connected to the pair of second external electrodes with intervening a part of the frame therebetween.

A pyroelectric device having a substrate and a first electrode overlying at least a portion of the substrate. A plurality of spaced apart nanometer sized pyroelectric elements are electrically connected to and extending outwardly from the first electrode so that each element forms a single domain. A dielectric material is deposited in the space between the individual elements and a second electrode spaced apart from said first electrode is electrically connected to said pyroelectric elements.

Integrated circuits with a molded package including a cavity and a semiconductor die spaced from an interior surface of the molded package within the cavity. The semiconductor die includes one or more electrical components, a thermal control component to control the temperature of the electrical component, and a driver to provide a current or voltage signal to the thermal control component at least partially according to a setpoint signal.

A vertical non-volatile memory device capable of stably maintaining an operating temperature in a chip level, a semiconductor package including the memory device, and a heat dissipation method of the memory device. The vertical non-volatile memory device includes a substrate on which a cell array area and an extension area are defined, a vertical channel structure formed on the substrate, a thermoelectric device including at least two semiconductor pillars formed on the substrate, and a stacked structure on the substrate. The stacked structure includes a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars. The at least two semiconductor pillars include an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.

A circuit includes a thermoelectric structure and an energy device. The thermoelectric structure includes a wire and p-type and n-type regions positioned on a front side of a substrate, the wire configured to electrically couple the p-type region to the n-type region, a first via configured to thermally couple the p-type region to a first power structure on a back side of the substrate, and a second via configured to thermally couple the n-type region to a second power structure on the back side of the substrate. The energy device is electrically coupled to each of the first and second power structures.

A wafer-level integrated thermal detector comprises a first wafer and a second wafer (W1, W2) bonded together. The first wafer (W1) includes a dielectric or semiconducting substrate (100), a dielectric sacrificial layer (102) deposited on the substrate, a support layer (104) deposited on the sacrificial layer or the substrate, a suspended active element (108) provided within an opening (106) in the support layer, a first vacuum-sealed cavity (110) and a second vacuum-sealed cavity (106) on opposite sides of the suspended active element. The first vacuum-sealed cavity (110) extends into the sacrificial layer (102) at the location of the suspended active element (108). The second vacuum-sealed cavity (106) comprises the opening of the support layer (104) closed by the bonded second wafer. The thermal detector further comprises front optics (120) for entrance of radiation from outside into one of the first and second vacuum-sealed cavities, aback reflector (112) arranged to reflect radiation back into the other one of the first and second vacuum-sealed cavities, and electrical connections (114) for connecting the suspended active element to a readout circuit (118).