A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.

A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.

A piezoelectric sensor and a manufacturing method therefor, and a detection apparatus, which relate to the technical field of sensing. The piezoelectric sensor includes: an array substrate: a first capping layer located on the array substrate and including a first portion and a second portion, wherein the first portion covers the array substrate, a cavity is provided between the second portion and the array substrate, and the second portion is provided with a first opening: a first electrode located above the first capping layer and above the cavity, a piezoelectric thin film located on the first electrode, and a second electrode located on the piezoelectric thin film.

Gallium nitride (GaN) integrated circuit technology with resonators is described. In an example, an integrated circuit structure includes a layer or substrate including gallium and nitrogen. A first plurality of electrodes is over the layer or substrate. A resonator layer is on the first plurality of electrodes, the resonator layer including aluminum and nitrogen. A second plurality of electrodes is on the resonator layer. Individual ones of the second plurality of electrodes are vertically over and aligned with corresponding individual ones of the first plurality of electrodes.

Multiple degenerately-doped silicon layers are implemented within resonant structures to control multiple orders of temperature coefficients of frequency.

In a chip-on-array approach, acoustic and electronic modules are separately formed. The acoustic stack is connected to one interposer, and the electronics are connected to another interposer. Different connection processes (e.g., using low temperature bonding for the acoustic stack and higher temperature-based interconnect for the electronics) may be used. This arrangement may allow for different pitches of the transducer elements and the I/O of the electronics by staggering vias in the interposers. The two interposers are then connected to form the chip-on-array.

Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.

According to one embodiment, a flexible substrate includes a line portion including a support plate including a first surface, a flexible insulating base located on the first surface and a wiring layer disposed on the insulating base, a piezoelectric material covering the line portion, a protective member located on the piezoelectric material and an island-shaped first electrode provided on the insulating base.

A thin-film bulk acoustic resonator, a semiconductor apparatus including the acoustic resonator and its manufacturing method are presented. The thin-film bulk acoustic resonator includes a lower dielectric layer, a first cavity inside the lower dielectric layer, an upper dielectric layer, a second cavity inside the upper dielectric layer, and a piezoelectric film that is located between the first and second cavities and continuously separates these two cavities. The plan views of the first and the second cavities have an overlapped region, which is a polygon that does not have any parallel sides. The piezoelectric film of this inventive concept is a continuous film without any through-hole in it, therefore it can offer improved acoustic resonance performance.

An exemplary embodiment of the present disclosure provides a multiplexer/demultiplexer, comprising a plurality of unit cells arranged in a lattice, a first domain, a second domain, a third domain, and a controller. Each of the unit cells can comprise a topological-insulative material, a first piezoelectric patch, and a second piezoelectric patch. A first domain can comprise a first portion of the plurality of unit cells. A second domain can comprise a second portion of the plurality of unit cells. A third domain can comprise a third portion of the plurality of unit cells. The controller can be configured to: apply a negative capacitance to the first piezoelectric patches in the first domain; apply a negative capacitance to the second piezoelectric patches in the second domain; and alternately apply a negative capacitance to the first and second piezoelectric patches, respectively, in the third domain.