Patent classifications
H10N52/00
CAMERA DEVICE
A camera device according to the present embodiment comprises: a first operation part comprising one of a first coil or a magnet and arranged on a fixed member; a second operation part which comprises the other one of the first coil and the magnet, is arranged on a movable member, and faces the first operation part; a hall sensor facing one of the first operation part and the second operation part; and a second coil arranged near the hall sensor, wherein at least a portion of the second coil is arranged between the hall sensor and the first coil.
SPIN-ORBIT TORQUE AND SPIN-TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY STACK
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a spin transfer torque (STT) magnetoresistive random access memory (MRAM) stack. The semiconductor structure may also include a spin orbit torque (SOT) MRAM stack vertically in series with the STT-MRAM. The SOT-MRAM stack may include a heavy metal spin hall effect rail configured to flip an SOT free-layer magnetic orientation in response to a horizontal signal through the heavy metal rail.
Magnetoresistive effect element and magnetic memory
A perpendicular magnetization type three-terminal SOT-MRAM that does not need an external magnetic field is provided. A magnetoresistance effect element where a first magnetic layer/nonmagnetic spacer layer/recording layer are disposed in order, and the first magnetic layer and the nonmagnetic spacer layer are provided to a channel layer.
SPIN INJECTION SOURCE, MAGNETIC MEMORY, SPIN HALL OSCILLATOR, COMPUTER, AND MAGNETIC SENSOR
According to one embodiment, a spin injection source comprising a half Heusler alloy-topological semi-metal that has a surface state of Dirac type and that is in contact with a ferromagnet. The half Heusler alloy-topological semi-metal supplies a spin current to the ferromagnet based on a current flowing in a direction parallel to a first surface that is in contact with the ferromagnet.
HALL SENSOR WITH PERFORMANCE CONTROL
A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.
STRESS REDUCTION LAYER BASED ON COATING TECHNIQUE
An integrated sensor and method for manufacturing the sensor includes a first component having a first material with a predetermined first value of coefficient of thermal expansion (CTE), and a second component over the first component. The second component includes a second material with a predetermined second value of CTE different from the first value. An interlayer is provided by molecular layer deposition, for minimizing stress caused by coefficient of thermal expansion mismatch between the first and second components. The interlayer includes an organic-inorganic hybrid polymer compound.
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device is disclosed. The semiconductor memory device may include a magnetic tunnel junction pattern, a spin-orbit torque (SOT) pattern in contact with a first portion of the magnetic tunnel junction pattern, a first transistor electrically connected to a second portion of the magnetic tunnel junction pattern and configured to be controlled by a first word line, and a second transistor electrically connected to a first end of the spin-orbit torque pattern and configured to be controlled by a second word line. An effective channel width of the first transistor may be different from an effective channel width of the second transistor.
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device is disclosed. The semiconductor memory device may include a magnetic tunnel junction pattern, a spin-orbit torque (SOT) pattern in contact with a first portion of the magnetic tunnel junction pattern, a first transistor electrically connected to a second portion of the magnetic tunnel junction pattern and configured to be controlled by a first word line, and a second transistor electrically connected to a first end of the spin-orbit torque pattern and configured to be controlled by a second word line. An effective channel width of the first transistor may be different from an effective channel width of the second transistor.
MAGNETIC FIELD-FREE SPIN-ORBIT TORQUE SWITCHING DEVICE USING SAPPHIRE MISCUT SUBSTRATE
Disclosed is a magnetic field-free spin-orbit torque switching device including a sapphire miscut substrate. More particularly, a spin-orbit torque switching device according to an embodiment includes a substrate having a step-terrace structure; and an input device formed on the substrate and provided with a heavy metal layer HM and a ferromagnetic layer FM.
MAGNETIC FIELD-FREE SPIN-ORBIT TORQUE SWITCHING DEVICE USING SAPPHIRE MISCUT SUBSTRATE
Disclosed is a magnetic field-free spin-orbit torque switching device including a sapphire miscut substrate. More particularly, a spin-orbit torque switching device according to an embodiment includes a substrate having a step-terrace structure; and an input device formed on the substrate and provided with a heavy metal layer HM and a ferromagnetic layer FM.