A cryogenic multilayer interconnect structure has a substrate including a molybdenum layer, a first insulating layer on the substrate and a first superconducting layer on the first insulating layer. The molybdenum layer has a coefficient of thermal expansion (CTE) that is well matched with the CTE of cryogenic electronic chips that are to be attached to the cryogenic multilayer interconnect structure. The substrate may be a copper clad molybdenum substrate that provide the CTE advantages provided by the molybdenum layer while also providing an increased thermal conductivity to improve the dissipation of heat generated by cryogenic electronic chips coupled to the substrate.

A quantum device according to an example embodiment includes: a quantum chip with a first surface and a second surface located on a side opposite to the first surface, in the quantum chip, at least a part of a qubit circuit being provided on the second surface; a first interposer with a third surface and a fourth surface located on a side opposite to the third surface, the first interposer being connected to the quantum chip in such a manner that the second surface of the quantum chip is opposed to the third surface of the first interposer; and a second interposer with a fifth surface and a sixth surface located on a side opposite to the fifth surface, the second interposer being connected to the first interposer in such a manner that the fourth surface of the first interpose is opposed to the fifth surface of the second interposer.

A stacked quantum computing device including: a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.

Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing. In yet another example, a bipolar-junction and complementary metal-oxide semiconductor stack construction can be employed.

An airbridge implements connections on a superconducting chip. It comprises a strip of superconductive material between a first superconductive area and a second superconductive area. A first end of said strip comprises a first planar end portion attached to and parallel with said first superconductive area, and a second end of said strip comprises a respective second planar end portion. A middle portion is located between said first and second planar end portions, forming a bend away from a plane defined by the surfaces of the first and second superconductive areas. First and second separation lines separate the end portions from the middle portion. At least one of said first and second separation lines is directed otherwise than transversally across said strip.

Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.

Methods for initializing a qubit into a pure state, reading the qubit, and arbitrarily rotating the qubit into any quantum state complete in times shorter than the qubit's typical dephasing and relaxation times. These methods provide universal single-qubit control and may be used to implement quantum gates with high fidelity. The methods may be implemented with superconducting qubits, such as heavy fluxonium, and do not rely on a three-dimensional cavity for suppressing spontaneous emission. Therefore, the methods may be implemented using smaller two-dimensional architectures commonly used for superconducting circuits. The methods also work with low-frequency qubits, i.e., qubits for which the energy spacing between the two quantum-computational states is less than the mean thermal energy of a surrounding bath. This reduces the cooling requirements of the qubit while maintaining fidelity.

Disclosed herein is a quantum processor comprising a substrate, a qubit structure formed on the substrate, an electroplated phonon downconversion material, and furrows through the electroplated phonon downconversion material forming a plurality of electroplated phonon downconversion islands coupled to the substrate configured to channel deposited energy away from the qubit structure. Also disclosed are methods of making and using the same.

A technique relates to configuring a superconducting router. The superconducting router is operated in a first mode. Ports are configured to be in reflection in the first mode in order to reflect a signal. The superconducting router is operated in a second mode. A given pair of the ports is connected together and in transmission in the second mode, such that the signal is permitted to pass between the given pair of the ports.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.