A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each of the select bit lines is electrically coupled to a gate of a corresponding second transistor. Each data storage element and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line. The controller turns ON the first transistor and a selected second transistor, and, while the first transistor and the selected second transistor are turned ON, applies different voltages to the bit line to perform corresponding different operations on the data storage element coupled to the selected second transistor.

Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.

A PCM cell includes a first electrode, a heater/PCM portion electrically connected to first electrode, the heater/PCM portion comprising a PCM material, a second electrode electrically connected to the PCM material, and an electrical insulator stack surrounding the projection liner. The stack includes a plurality of first layers comprised of a first material and having a plurality of first inner sides facing towards the projection liner, and a plurality of second layers alternating with the plurality of first layers, the plurality of second layers comprised of a second material that is different from the first material, and the second plurality of layers having a plurality of second inner sides facing towards the projection liner. The plurality of second inner sides that are offset from the plurality of first inner sides forming a plurality of gaps.

A resistive memory device includes a bottom electrode, a switching layer including a first horizontal portion, a second horizontal portion over an upper surface of the bottom electrode, and a first vertical portion over a side surface of the bottom electrode, a top electrode including a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer, and a conductive via contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode. By providing a switching layer and a top electrode which conform to a non-planar profile of the bottom electrode, charge crowding and a localized increase in electric field may facilitate resistance-state switching and provide a reduced operating voltage.

A memory device is provided with a support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between a first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resist memory cells are arranged.

The present disclosure discloses a method for manufacturing a resistive switching element, including: performing an etching process, a deposition process and a polishing process alternately to prepare the bottom electrode, the resistive switching layer and the top electrode; and optimizing at least one of the bottom electrode, the resistive switching materials and the oxygen storage layer by using the sidewall process when preparing the bottom electrode and the resistive switching materials, so as to reduce a contact area between the bottom electrode and the resistive switching materials, and/or reduce a contact area between the resistive switching materials and the oxygen storage layer. The method could form conductive filaments in the resistive switching layer, and a low resistive state and high resistive state are realized by forming and breaking conductive filaments. The present disclosure further discloses a resistive switching element and a resistive switching memory having the resistive switching element.

A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first and second layers differ. The first and second pluralities of conductive lines are each lithographically defined. The first and second pluralities of conductive lines are insulated from each other. The memristive interlayer connectors are memristively coupled with a first portion of the first plurality of conductive lines and memristively coupled with a second portion of the second plurality of conductive lines. The memristive interlayer connectors are thus sparsely coupled with the first and second pluralities of conductive lines. Each memristive interlayer connector includes a conductive portion and a memristive portion. The memristive portion is between the conductive portion and corresponding line(s) of the first plurality of conductive lines and/or the second plurality of conductive lines.

A microelectronic device comprises pillar structures extending vertically through an isolation material, conductive lines electrically coupled to the pillar structures, contact structures between the pillar structures and the conductive lines, and interconnect structures between the conductive lines and the contact structures. The conductive lines comprise one or more of titanium, ruthenium, aluminum, and molybdenum. The interconnect structures comprise a material composition that is different than one or more of a material composition of the contact structures and a material composition of the conductive lines. Related memory devices, electronic systems, and methods are also described.

According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH.sub.3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O.sub.2 as the etching reactant and an inert gas such as N.sub.2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.