Provided is a multi-negative differential resistance device. The multi-negative differential resistance device includes a first negative differential resistance device and a second negative differential resistance device connected in parallel with the first negative differential resistance device, and a peak and a valley of the first negative differential resistance device and a peak and a valley of the second negative differential resistance device are synthesized, and, thus, the multi-negative differential resistance device has two peaks and two valleys.

A negative differential resistance (NDR) device for non-volatile memory cells in crossbar arrays is provided. Each non-volatile memory cell is situated at a crosspoint of the array. Each non-volatile memory cell comprises a switching layer in series with an NDR material containing fast diffusive atoms that are electrochemically inactive. The switching layer is positioned between two elec-trodes.

An elementary cell includes a device and a non-volatile resistive memory mounted in a series, the device including an upper selector electrode, a lower selector electrode, a layer made up of a first active material, referred to as an active selecting layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made of at least a second active material, referred to as an active memory layer, the active selecting layer being in a conductive crystalline state and the memory being in a very strongly resistive state that is more resistive than the strongly resistive state of the memory.

An elementary cell includes a device and a non-volatile resistive memory mounted in a series, the device including an upper selector electrode, a lower selector electrode, a layer made up of a first active material, referred to as an active selecting layer, the device being intended to form a volatile selector; the memory including an upper memory electrode, a lower memory electrode, a layer made of at least a second active material, referred to as an active memory layer, the active selecting layer being in a conductive crystalline state and the memory being in a very strongly resistive state that is more resistive than the strongly resistive state of the memory.

The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a metal insulator metal (MIM) device including a metal ion-doped insulating layer and configured to perform integration and fire, and the MIM device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.

The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a metal insulator metal (MIM) device including a metal ion-doped insulating layer and configured to perform integration and fire, and the MIM device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.

Gunn diodes are included in a device plane of an integrated circuit device, e.g., a diode array is in the same plane as a transistor array. A Gunn diode includes two highly n-doped regions surrounding a lower-doped n-type region. The highly-doped regions may be formed through epitaxial deposition. A Gunn diode may be arranged as a vertical diode, with two contacts stacked vertically over and under the diode, or as a horizontal diode, with two contacts at opposite horizontal ends of the diode. The Gunn diodes may be formed around a fin, e.g., with a front-side contact over the fin and a back-side contact under the fin.

Disclosed herein are clock synchronization circuits using Gunn diodes, and related integrated circuit (IC) structures, devices, and techniques. In one aspect, an IC structure includes a first transistor, a second transistor, a first Gunn diode coupled to the first transistor, a second Gunn diode coupled to the second transistor, and a third transistor coupled between the first Gunn diode and the second Gunn diode.

Disclosed herein are clock synchronization circuits using Gunn diodes, and related integrated circuit (IC) structures, devices, and techniques. In one aspect, an IC structure includes a first transistor, a second transistor, a first Gunn diode coupled to the first transistor, a second Gunn diode coupled to the second transistor, and a third transistor coupled between the first Gunn diode and the second Gunn diode.