H10N99/00

INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF INFORMATION PROCESSING APPARATUS

An information processing apparatus includes a converting portion having a plurality of electrical conductors to be arranged in mutual separation and a medium arranged so as to mutually connect the plurality of electrical conductors, wherein the converting portion is the information processing apparatus to convert an input signal to an output signal. The medium includes the electrolyte and is configured to be capable of controlling an electrical conductivity of an electrically conductive path mutually electrically connecting the plurality of electrical conductors, and the medium is selected such that the electrical conductivity of the electrically conductive path changes over time with the input signal not being present.

LAMINATED BATTERY
20190334155 · 2019-10-31 ·

A laminated battery according to the present invention is a secondary battery where a first sheet battery, a second sheet battery, a third sheet battery, and a fourth sheet battery are laminated in this order. When an X-Y plane is viewed from above, a tab part of the first sheet battery is placed projecting outward of the sheet battery, and a tab part of the fourth sheet battery is placed projecting outward of the third sheet battery. A second electrode on a surface of the first tab part and a second electrode on a surface of the fourth tab part tab part, are placed face-to-face with each other and connected.

CIRCUIT ELEMENT, STORAGE DEVICE, ELECTRONIC EQUIPMENT, METHOD OF WRITING INFORMATION INTO CIRCUIT ELEMENT, AND METHOD OF READING INFORMATION FROM CIRCUIT ELEMENT

[Object] To provide a circuit element, a storage device, electronic equipment, a method of writing information into a circuit element, and a method of reading information from a circuit element. [Solution] The circuit element includes: paired inert electrodes; and a switch layer provided between the paired inert electrodes, configured to function as a selection element and a storage element as a single layer, and having a differential negative resistance region in a current-voltage characteristic.

SEMICONDUCTOR SOLID STATE BATTERY

A semiconductor solid state battery has an insulating layer provided between an N-type semiconductor and a P-type semiconductor. The first insulating layer preferably has a thickness of 3 nm to 30 m and a dielectric constant of 10 or less. The first insulating layer preferably has a density of 60% or more of a bulk body. The semiconductor layer preferably has a capture level introduced. The semiconductor solid state battery can eliminate leakage of an electrolyte solution.

Interconnect structure and method for on-chip information transfer

An interconnect structure for on-chip information transfer, and a method for on-chip information transfer. The interconnect structure comprises a source configured for electrically generating plasmons; a detector configured for electrically detecting the generated plasmons; and a plasmonic waveguide coupled between the source and the detector.

ULTRASENSITIVE SENSOR BASED ON A PIEZOELECTRIC TRANSISTOR
20190265181 · 2019-08-29 ·

Chemical sensors include a functionalized electrode configured to change surface potential in the presence of an analyte. A piezoelectric element is connected to the functionalized electrode. A piezoresistive element is in contact with the piezoelectric element.

ULTRASENSITIVE SENSOR BASED ON A PIEZOELECTRIC TRANSISTOR
20190265182 · 2019-08-29 ·

Methods of using and making chemical sensors include exposing a functionalized electrode to a substance to be tested. The functionalized electrode is electrically connected to a sensor having a piezoelectric element and a piezoresistive element. A voltage on the functionalized electrode controls a resistance of the piezoresistive element. A current is measured passing through the piezoresistive element. The presence of the analyte is determined based on the measured current.

Secondary cell and method for manufacturing secondary cell

The present invention provides a method for manufacturing a secondary cell having a plurality of unit cells 21 that are connected in parallel, including, a step to prepare sheet-shaped unit cells each having a structure that a first electrode layer, a metal oxide semiconductor layer, a charging layer, and a second electrode layer are layered, a step to form a cell sheet by connecting the laminated unit cells in parallel, a step to measure a capacity of the cell sheet, and a step to connect a unit cell for capacity adjustment to the cell sheet in parallel when the capacity is smaller than a specification value.

Method for manufacturing secondary cell

A method for manufacturing a secondary cell, the secondary cell including a charging layer that captures electrons by forming energy levels in a band gap by causing a photoexcited structural change in an n-type metal oxide semiconductor coated with an insulating material, includes a coating step to coat a coating liquid so as to form a coating film that includes constituents that will form the charging layer; a drying step to dry the coating liquid coated in the coating step; a UV irradiating step to form a UV-irradiated coating film by irradiating the dried coating film obtained through the drying step with ultraviolet light; and a burning step to burn a plurality of the UV-irradiated coating films, after forming the plurality of UV-irradiated coating films by repeating a set plural times, the set including the coating step, the drying step, and the UV irradiating step.

SEMICONDUCTOR DEVICE
20190228828 · 2019-07-25 ·

Provided is a semiconductor device having a plurality of memory cells (MC1 and MC2), in which each of the plurality of memory cells (MC1 and MC2) includes: a memory transistor (10M) having an oxide semiconductor layer (17M) as an active layer; and a first selection transistor (10S) having a crystalline silicon layer (13S) as the active layer and connected to the memory transistor (10M) in series.