In a display device having a non-rectangular display unit, occurrence of a difference in luminance between a region with a high load and a region with a low load is suppressed. A region inside the display unit is segmented into a high-load region with a high load on horizontal scanning lines (an initialization control line and a write control line) and a low-load region with a low load on horizontal scanning lines. An initialization control line and a write control line that are disposed in the high-load region are driven by a discharge driver and a scan driver, respectively. An initialization control line and a write control line that are disposed in the low-load region both are driven by, for example, the discharge driver.

A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

A display device includes a pixel unit including first pixels disposed in a first area and second pixels disposed in a second area, an emission driver configured to sequentially supply emission signals of a turn-off level to the first pixels and the second pixels based on a first start signal, a first clock signal, and a second clock signal, and a first scan driver configured to sequentially supply first scan signals of a turn-on level to the first pixels based on a second start signal, the first clock signal, and the second clock signal, and sequentially supply the first scan signals of the turn-on level to the second pixels based on a third start signal, the first clock signal, and the second clock signal.

Provided are a display panel and a display device. The display panel includes multiple cascaded gate drive units. Each gate drive unit includes a shift register unit and an inverted unit. The inverted unit is electrically connected to the shift register unit. A scan output terminal of the shift register unit is electrically connected to one scan line. An inverted scan output terminal of the inverted unit is electrically connected to one inverted scan line. The scan output terminal of the shift register unit outputs a first effective pulse signal. The inverted scan output terminal of the inverted unit outputs a second effective pulse signal. A time period corresponding to the first effective pulse signal at least partially overlaps a time period corresponding to the second effective pulse signal, and the type of the first effective pulse signal is opposite to the type of the second effective pulse signal.

A manufacturing method of an electronic device and an electronic device are provided. The manufacturing method includes the following steps: providing a substrate; forming a plurality of signal lines and a testing circuit on the substrate, wherein the testing circuit includes a plurality of output channels electrically connected to at least a portion of the plurality of signal lines; performing a testing process; and optionally isolating the testing circuit from the at least a portion of the plurality of signal lines. The testing process includes: providing a signal; processing a plurality of testing signals by processing the signal via the testing circuit; and transmitting the plurality of testing signals to the at least a portion of the plurality of signal lines via the plurality of output channels. The plurality of output channels are less than the plurality of signal lines in quantity.

A display driving module, a display driving method, and a display device are provided. The display driving module includes a clock signal line, a clock signal generating circuit and a gate driving circuit, where the gate driving circuit includes multiple stages of gate driving units; the clock signal generating circuit is electrically connected to the clock signal line and is configured to generate at least two clock signals and provide different clock signals to the clock signal line in a time-sharing manner; the gate driving unit is electrically connected to the clock signal line and configured to generate a gate driving signal according to the clock signals on the clock signal line; when potentials of the clock signals are valid voltages, the potentials of different clock signals are different.

A display device includes a display panel, a display driver integrated circuit and a driving control circuit. The display panel includes a plurality of pixels connected to a plurality of driving lines and a plurality of source lines. The display driver integrated circuit includes a driving control signal generator. The driving control signal generator generates a driving control signal based on display device information and pixel values corresponding to at least a portion of the plurality of rows among a plurality of previous pixel values of a previous frame and a plurality of present pixel values of a present frame. The driving control circuit selectively connects the display driver integrated circuit with each of the plurality of driving lines based on the driving control signal such that first driving signals provided to first driving lines among the plurality of driving lines are blocked.

An example method includes programming, during non-emission periods of frames of a plurality of frames based on image data of the frames, pixels of the plurality of pixels of a display of a computing device; causing, during emission periods of the frames, pixels of the plurality of pixels to emit light, wherein an amount of light emitted by the pixels during an emission period of a particular frame is based on the programming for the particular frame; and synchronizing operation of one or more sensors and operation of the plurality of pixels by at least causing the one or more sensors to alternatingly emit, through the display, electromagnetic radiation during emission periods and non-emission periods.

An example method includes programming, based on image data of a frame of a plurality of frames and during a non-emission period of the frame, pixels of a plurality of pixels of a display of a computing device; causing pixels of the plurality of pixels to emit light during an emission period of the frame, wherein an amount of light emitted by the pixels during the emission period is based on the programming; and synchronizing operation of one or more sensors and operation of the plurality of pixels by at least causing the one or more sensors to emit, during a particular portion of the emission period of the frame, electromagnetic radiation through the display.

A display system includes a first memory and a display driver. The display system is configured to control the first memory to receive compensation information from the first memory with a first frequency and generate data signals for image data to be displayed on a display panel. The generation of the data signals comprises performing a compensation for the data signals based on the compensation information received from the first memory. The display driver is further configured to update pixels of the display panel with the data signals during an active display state. The display driver is further configured to generate updated compensation information based at least in part on the image data and the compensation information received from the first memory and transmit the updated compensation information to the first memory during the active display state with a second frequency lower than the first frequency.