Methods, systems, and apparatus to facilitate a fault triggered diode emulation mode of a transistor. An example apparatus includes a driver to output a control signal to a gate terminal of a transistor of a power converter; and a diode emulation control circuit to, in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor.

A method and system for suppressing EMP-induced voltage surges due to detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. Surge protection assemblies are positioned intermediate a signal stream and a plurality of electronic device ports associated with a plurality of communication channels of networked devices. Single-channel multimode surge suppressing systems are combined to form multi-port multimode protection systems that connect directly to multiport networked devices supporting communication channels with mixed signals data and direct current power in Gigabit Ethernet networks supporting PoE. The surge suppressing systems mitigate differential and common mode induced interference and protect from overvoltage surges associated with E1, E2, and E3 components of the HEMP and mitigate the over-voltages to predetermined allowable levels within the predetermined time. The surge suppressing systems is interoperable with multimode PoE and support endpoint and midspan PoE devices of Gigabit networks.

A method and system for suppressing EMP-induced voltage surges due to detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. Surge protection assemblies are positioned intermediate a signal stream and a plurality of electronic device ports associated with a plurality of communication channels of networked devices. Single-channel multimode surge suppressing systems are combined to form multi-port multimode protection systems that connect directly to multiport networked devices supporting communication channels with mixed signals data and direct current power in Gigabit Ethernet networks supporting PoE. The surge suppressing systems mitigate differential and common mode induced interference and protect from overvoltage surges associated with E1, E2, and E3 components of the HEMP and mitigate the over-voltages to predetermined allowable levels within the predetermined time. The surge suppressing systems is interoperable with multimode PoE and support endpoint and midspan PoE devices of Gigabit networks.

A 0U, rack-mounted, power distribution, environment monitoring, and fire-protection apparatus including an environmental monitoring sensor system, including a fire detection and protection system located in a computer rack. The invention includes a system to localize damage to equipment, business interruption, and hazardous conditions to a computer rack.

A 0U, rack-mounted, power distribution, environment monitoring, and fire-protection apparatus including an environmental monitoring sensor system, including a fire detection and protection system located in a computer rack. The invention includes a system to localize damage to equipment, business interruption, and hazardous conditions to a computer rack.

A method and system for suppressing EMP-induced voltage surges due to detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. Surge protection assemblies are positioned intermediate a signal stream and a plurality of electronic device ports associated with a plurality of communication channels of networked devices. Single-channel multimode surge suppressing systems are combined to form multi-port multimode protection systems that connect directly to multiport networked devices supporting communication channels with mixed signals data and direct current power in Gigabit Ethernet networks supporting PoE. The surge suppressing systems mitigate differential and common mode induced interference and protect from overvoltage surges associated with E1, E2, and E3 components of the HEMP and mitigate the over-voltages to predetermined allowable levels within the predetermined time. The surge suppressing systems is interoperable with multimode PoE and support endpoint and midspan PoE devices of Gigabit networks.

A method and system for suppressing EMP-induced voltage surges due to detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. Surge protection assemblies are positioned intermediate a signal stream and a plurality of electronic device ports associated with a plurality of communication channels of networked devices. Single-channel multimode surge suppressing systems are combined to form multi-port multimode protection systems that connect directly to multiport networked devices supporting communication channels with mixed signals data and direct current power in Gigabit Ethernet networks supporting PoE. The surge suppressing systems mitigate differential and common mode induced interference and protect from overvoltage surges associated with E1, E2, and E3 components of the HEMP and mitigate the over-voltages to predetermined allowable levels within the predetermined time. The surge suppressing systems is interoperable with multimode PoE and support endpoint and midspan PoE devices of Gigabit networks.

A data interconnect system includes: a plurality of pins arranged within a receptacle, a first one of the pins being a power pin, wherein the pins are electrically isolated from each other within the receptacle; a first switching network including a first plurality of parallel switching devices, each of the parallel switching devices of the first plurality of parallel switching devices coupling a respective one of the pins to a node; a first current path from the node to ground, the first current path including a current device; and a second current path, parallel to the first current path, the second current path including a resistor coupling the node to ground.

A data interconnect system includes: a plurality of pins arranged within a receptacle, a first one of the pins being a power pin, wherein the pins are electrically isolated from each other within the receptacle; a first switching network including a first plurality of parallel switching devices, each of the parallel switching devices of the first plurality of parallel switching devices coupling a respective one of the pins to a node; a first current path from the node to ground, the first current path including a current device; and a second current path, parallel to the first current path, the second current path including a resistor coupling the node to ground.

A system and method for protecting an electronics module on a spacecraft in space are described. The system includes a non-radiation hardened electronics module electrically connected to a power supply, with a switch connected between the power supply and the electronics module. The switch can disconnect the electronics module from the power supply in response to an event signal. A sensor which is capable of detecting a solar proton event is connected to the switch. The sensor emits the event signal upon detection of the solar proton event.