In some embodiments, there is provided an apparatus including a common bus and a plurality of oscillatrode circuits coupled to the common bus, the plurality of oscillatrode circuits including a first oscillatrode circuit outputting a first frequency tone when a first input voltage is detected by the first oscillatrode circuit and a second oscillatrode circuit outputting a second frequency tone when a second input voltage is detected by the second oscillatrode circuit, wherein common bus carries the first frequency tone and the second frequency tone at different frequencies in a frequency division multiplex signal. Related systems, methods, and articles of manufacture are also disclosed.

A frequency modulator includes a first pair of diodes with two capacity diodes, and a second pair of diodes with two additional capacity diodes. The second pair of diodes is employed in parallel. The frequency modulator also includes a first modulator input for reception of a first modulation signal and a second modulator input for reception of a symmetrical second modulation signal. Both pairs of diodes are coupled to an oscillator unit.

A frequency modulator includes a first pair of diodes with two capacity diodes, and a second pair of diodes with two additional capacity diodes. The second pair of diodes is employed in parallel. The frequency modulator also includes a first modulator input for reception of a first modulation signal and a second modulator input for reception of a symmetrical second modulation signal. Both pairs of diodes are coupled to an oscillator unit.

A charger including a class E power driver, a frequency-shift keying (“FSK”) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.

A charger including a class E power driver, a frequency-shift keying (“FSK”) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.

A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

There is provided a method for processing a set of input symbols. The method is performed by a transmitter. The method comprises acquiring a set of input symbols. The method comprises generating a set of precoded symbols from the set of input symbols by subjecting the set of input symbols to a coding vector. The method comprises generating a transmission signal comprising a sequence of pulse forms from the set of precoded symbols by pulse shaping the set of precoded symbols. The coding vector is based on a model vector modelling intersymbol interference experienced by the pulse forms.

Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

A wireless data transmitter including: a data modulator adapted to modulate a data signal based on a frequency signal; and at least one antenna adapted to wirelessly transmit the modulated data signal and the frequency signal independently.