The invention relates to a tunable, silicon-based negative-resistance circuit (10, 30) and to an active filter (50) for E-band frequencies (60 to 90 GHz). A base of a transistor (11) is connected to an on-chip inductive transmission line (13) which has a length of approximately a quarter-wavelength at a frequency of 83.5 GHz. The transmission line connects a DC voltage source (14) to the base terminal of the transistor (11) in order to bias the base. Another DC voltage source (15) is connected to the collector of the transistor (11) to bias the transistor. A capacitor (16) operatively bypasses or decouples the voltage source (15) in order to shunt high frequencies or alternating current (AC) signals to ground. The emitter terminal of the transistor (11) is connected to ground through a resistor (18) to limit the collector current (l.sub.e). The circuit gives rise to improved quality factor of resonators.

A method of stabilizing a variable filter for an analog electromagnetic signal against circuit oscillation includes the steps of: providing a signal loop comprising a signal input, a signal output, and a plurality of variable circuit elements connected in the signal loop, the plurality of variable circuit elements comprising an adjustable resonator and an adjustable gain block, the signal loop having a variable frequency response that is characterized by a central frequency, a frequency passband, a response Q, and an operating point and a resonator response curve that are plottable in a Cartesian s-plane having an origin, a real axis, and an imaginary axis; and maintaining stability of the variable filter within an operating range by controlling the adjustable resonator and the adjustable gain block such that, in the Cartesian s-plane, the resonator response curve satisfies an orthogonality stability condition.

Aspects of the present disclosure include systems, methods, devices, and circuits for correcting integral non-linearity using a hybrid phase interpolator. Consistent with some embodiments, a circuit comprises a first and second phase interpolator mixer connected to an injection-locked ring. The first phase interpolator mixer provides a first injection signal to the injection-locked ring based on a clock signal, and the second phase interpolator mixer provides a second injection signal to the injection-locked ring. The first and second injection signals have inverse step size profiles. The injection-locked ring generates a first and second output clock phase based on the first and second injection signals. In generating the first and second output clock phases, the injection-locked ring averages the step size profiles of the first and second injection signals.

A variable filter for an RF circuit has a signal loop comprising a signal input port and a signal output port, and a plurality of circuit elements connected within the signal loop. The plurality of circuit elements comprise a multi-pole resonator comprising a plurality of frequency tunable resonators and an adjustable scaling block that applies a gain factor. Adjacent frequency tunable resonators within the multi-pole resonator are reciprocally coupled. A controller is connected to tune the multi-pole resonator and to adjust the gain factor of the adjustable scaling block such that the signal loop generates a desired bandpass response.

An antenna comprising: a driven element; an input feed coupled to the driven element wherein the input feed is configured to be connected to a receiver; a non-Foster circuit having a negative impedance, wherein the non-Foster circuit is configured to actively load the antenna at a location on the antenna other than at the input feed; and wherein the antenna fits within an imaginary sphere having a radius a, and wherein the product ka is less than 0.5, where k is a wave number.

An antenna comprising: a driven element; an input feed coupled to the driven element wherein the input feed is configured to be connected to a receiver; a non-Foster circuit having a negative impedance, wherein the non-Foster circuit is configured to actively load the antenna at a location on the antenna other than at the input feed; and wherein the antenna fits within an imaginary sphere having a radius a, and wherein the product ka is less than 0.5, where k is a wave number.

A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal.

The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.

The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.

A negative impedance circuit including: a first and a second bipolar transistors having a common collector, a base of the first transistor being connected to an emitter of the second transistor; a third and a fourth bipolar transistors having a common collector, a base of the third transistor being connected with an emitter of the fourth transistor, and at least one first impedance formed of one or of a plurality of passive components coupling the common collector of the first and second transistors to the common collector of the third and fourth transistors, a base of the second transistor being coupled to the collector of the third and fourth transistors and a base of the fourth transistor being coupled to the collector of the first and second transistors.