An SOI semiconductor structure, including a substrate layer formed on a back side and a semiconductor layer of a second conductivity type formed on a front side, an insulating layer being disposed between the substrate layer and the semiconductor layer, a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body being formed in the semiconductor layer, and the semiconductor body extending from an underside up to the front side, at least three first metallic terminal contacts being formed on the upper side, and at least three second metallic terminal contacts being formed on the underside, the first terminal contacts being offset with respect to the second terminal contacts in a projection perpendicular to the front side, each first terminal contact and each second terminal contact being formed in each case on a highly doped semiconductor contact region of a second conductivity type.

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

Some embodiments relate to a probabilistic random number generator. The probabilistic random number generator includes a memory cell comprising a magnetic tunnel junction (MTJ), and an access transistor coupled to the MTJ of the memory cell. A variable current source is coupled to the access transistor and is configured to provide a plurality of predetermined current pulse shapes, respectively, to the MTJ to generate a bit stream that includes a plurality of probabilistic random bits, respectively, from the MTJ. The predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities for the MTJ.

The present disclosure provides a domain wall magnetic tunnel junction device. Integration of input spikes pushes a domain wall within a ferromagnetic track toward a magnetic tunnel junction (MTJ). An energy gradient within the track pushes the domain wall away from the MTJ by leaking accumulated energy from the input spikes. If the integrated input spikes exceed the energy leak of the gradient within a specified time period, the domain wall reaches the MTJ and reverses its resistance, producing an output spike. The leaking energy gradient can be created by a magnetic field, a trapezoidal shape of the ferromagnetic track, or nonuniform material properties in the ferromagnetic track.

A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.

A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.

An apparatus is provided to improve spin injection efficiency from a magnet to a spin orbit coupling material. The apparatus comprises: a first magnet; a second magnet adjacent to the first magnet; a first structure comprising a tunneling barrier; a third magnet adjacent to the first structure; a stack of layers, a portion of which is adjacent to the third magnet, wherein the stack of layers comprises spin-orbit material; and a second structure comprising magnetoelectric material, wherein the second structure is adjacent to the first magnet.

A tunneling magnetoresistance (TMR) sensor device is disclosed that includes four or more TMR resistors. The TMR sensor device comprises a first TMR resistor comprising a first TMR film, a second TMR resistor comprising a second TMR film different than the first TMR film, a third TMR resistor comprising the second TMR film, and a fourth TMR resistor comprising the first TMR film. The first, second, third, and fourth TMR resistors are disposed in the same plane. The first TMR film comprises a synthetic anti-ferromagnetic pinned layer having a magnetization direction of the reference layer orthogonal to a free layer. The second TMR film comprises a double synthetic anti-ferromagnetic pinned layer having a magnetization direction of the reference layer orthogonal to the magnetization of a free layer, but opposite to the magnetization direction of the reference layer of the first TMR film.

A magnetic field detection apparatus includes a magnetoresistive effect element and a helical coil. The magnetoresistive effect element includes a magnetoresistive effect film extending in a first axis direction. The helical coil includes a parallel connection including first and second parts extending in a second axis direction inclined with respect to the first axis direction. The first and second parts are adjacent to each other in a third axis direction and coupled to each other in parallel. The helical coil is wound around the magnetoresistive effect element while extending along the third axis direction. The magnetoresistive effect film overlaps the first and second parts in a fourth axis direction orthogonal to the second and third axis directions. The helical coil is configured to be supplied with a current and thereby configured to generate an induction magnetic field to be applied to the magnetoresistive effect film in the third axis direction.

A magnetic sensor includes first to fourth resistor sections and a plurality of MR elements. Each of the plurality of MR elements belongs to any of first to fourth groups. The first to fourth groups are defined based on the areas of top surfaces of the MR elements. The first resistor section, the second resistor section, the third resistor section, and the fourth resistor section are constituted of the first group, the second group, the third group, and the fourth group, respectively; the second group, the first group, the fourth group, and the third group, respectively; the first group, the fourth group, the third group, and the second group, respectively; or the third group, the second group, the first group, and the fourth group, respectively.