C23C16/0209

PARTICLE COATING METHOD
20210156025 · 2021-05-27 ·

A particle coating method includes a heating step of heating soft magnetic metal particles containing an amorphous phase within a temperature range of 100° C. or higher and 500° C. or lower for 0.1 hours or more and 300 hours or less, and an insulating film formation step of forming an insulating film at surfaces of the soft magnetic metal particles by a chemical vapor deposition method. The soft magnetic metal particles preferably contain the amorphous phase at 50 vol % or more.

MASKING BLOCK THAT IS EASILY BONDABLE AND DEBONDABLE, METHOD FOR MANUFACTURING MASKING BLOCK AND METHOD FOR FORMING PATTERN OF TWO-DIMENSIONAL MATERIAL USING MASKING BLOCK

A masking block includes a base substrate, a gamma-alumina thin film disposed on the base substrate, and a hexagonal boron nitride thin film doped with carbon and oxygen and disposed on the gamma-alumina thin film. An amount of carbon in the hexagonal boron nitride thin film is 1 at % to 15 at %.

SYSTEMS AND METHODS FOR GROWTH OF SILICON CARBIDE OVER A LAYER COMPRISING GRAPHENE AND/OR HEXAGONAL BORON NITRIDE AND RELATED ARTICLES

Systems and methods for growth of silicon carbide over a layer comprising graphene and/or hexagonal boron nitride, and related articles, are generally described. In some embodiments, a SiC film is fabricated over a layer comprising graphene and/or hexagonal boron nitride, which in turn is disposed over a substrate. The layer and/or the substrate may be lattice-matched with the SiC film to reduce defect density in the SiC film. The fabricated SiC film may then be removed from the substrate via, for example, a stressor attached to the SiC film. In certain cases, the layer serves as a reusable platform for growing SiC films and also serves a release layer that allows fast, precise, and repeatable release at the layer surface.

Substrate processing apparatus and manufacturing method of semiconductor device

A substrate processing a technology including: a substrate holder; a tubular reactor that houses the substrate holder; an inlet flange connected to the tubular reactor including a plurality of gas introduction ports; a lid that closes a lower opening of the inlet flange in a manner such that the substrate holder can be carried in and out; heater elements disposed along the outer peripheral surface of the inlet flange while avoiding the gas introduction ports; temperature sensors thermally coupled to the inlet flange or any heater element and adapted to detect temperatures; and a temperature controller that divides of the heater elements into groups and controls power supply to the respective heater elements independently for each of the groups based on temperatures detection temperatures detected by the temperature sensors.

GROUP III NITRIDE SINGLE CRYSTAL SUBSTRATE
20230407521 · 2023-12-21 · ·

A group III nitride single crystal substrate including a main surface, the main surface including: a center; a periphery; an outer region whose distance from the center is greater than 30% of a first distance, the first distance being a distance from the center to the periphery; and an inner region whose distance from the center is no more than 30% of the first distance, wherein a ratio (v.sub.Av.sub.B)/v.sub.B is within the range of 0.1%, wherein v.sub.A is a minimum value of peak wave numbers of micro-Raman spectra in the inner region; and v.sub.B is an average value of peak wave numbers of micro-Raman spectra in the outer region.

PROCESS FOR MANUFACTURING A SILICON CARBIDE COATED BODY
20210062336 · 2021-03-04 ·

The present invention relates to a new process for manufacturing a silicon carbide (SiC) coated body by depositing SiC in a chemical vapor deposition method using dimethyldichlorosilane (DMS) as the silane source on a graphite substrate. A further aspect of the present invention relates to the new silicon carbide coated body, which can be obtained by the new process of the present invention, and to the use thereof for manufacturing articles for high temperature applications, susceptors and reactors, semiconductor materials, and wafer.

Group III nitride semiconductor substrate and method of manufacturing group III nitride semiconductor substrate
10947641 · 2021-03-16 · ·

There is provided a group III nitride semiconductor substrate (free-standing substrate (30)) that is formed of a group III nitride semiconductor crystal and has a thickness of 300 m or more and 1000 m or less. Both exposed first and second main surfaces in a relationship of top and bottom are semipolar planes. A difference in a half width of an X-ray rocking curve (XRC) measured by making X-rays incident on each of the first and second main surfaces in parallel to an m axis of the group III nitride semiconductor crystal is 500 arcsec or less.

Formation of crystalline, layered transition metal dichalcogenides

Embodiments of the present disclosure relate to forming a two-dimensional crystalline dichalcogenide by positioning a substrate in an annealing apparatus. The substrate includes an amorphous film of a transition metal and a chalcogenide. The film is annealed at a temperature from 500 C. to 1200 C. In response to the annealing, a two-dimensional crystalline structure is formed from the film. The two-dimensional crystalline structure is according to a formula MX.sub.2, M includes one or more of molybdenum (Mo) or tungsten (W) and X includes one or more of sulfur (S), selenium (Se), or tellurium (Te).

METHODS FOR FORMING PROTECTIVE COATINGS CONTAINING CRYSTALLIZED ALUMINUM OXIDE

Embodiments of the present disclosure generally relate to protective coatings on substrates and methods for depositing the protective coatings. In one or more embodiments, a method of forming a protective coating on a substrate includes depositing a chromium oxide layer containing amorphous chromium oxide on a surface of the substrate during a first vapor deposition process and heating the substrate containing the chromium oxide layer comprising the amorphous chromium oxide to convert at least a portion of the amorphous chromium oxide to crystalline chromium oxide during a first annealing process. The method also includes depositing an aluminum oxide layer containing amorphous aluminum oxide on the chromium oxide layer during a second vapor deposition process and heating the substrate containing the aluminum oxide layer disposed on the chromium oxide layer to convert at least a portion of the amorphous aluminum oxide to crystalline aluminum oxide during a second annealing process.

SELECTIVE SURFACE FINISHING FOR CORROSION INHIBITION VIA CHEMICAL VAPOR DEPOSITION
20210071308 · 2021-03-11 ·

A versatile, thermally stable and economically effective corrosion inhibition treatment for copper (Cu) metal and selected metals surface through a single step chemical vapor deposition (CVD) of selected inhibitor compounds at temperatures as low as 100-200 C. is described in this invention. The resulting CVD deposited inhibition coating is thermally stable to 300 C. and protects Cu and selected metals from active corrosion in various technologically important operational environments. The selective coating for copper metal is achieved by controlling the chemistry of bonding between the Copper metal surface and inhibitor material used. The technique can be accomplished by using one or more inhibitors separately or in combination in order to create an all-terrain stable & robust corrosion prevention coating for copper metal.