Patent classifications
C23C16/30
METHODS FOR SELECTIVE DEPOSITION UTILIZING N-TYPE DOPANTS AND/OR ALTERNATIVE DOPANTS TO ACHIEVE HIGH DOPANT INCORPORATION
A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.
METHODS FOR SELECTIVE DEPOSITION UTILIZING N-TYPE DOPANTS AND/OR ALTERNATIVE DOPANTS TO ACHIEVE HIGH DOPANT INCORPORATION
A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.
FILM-FORMING METHOD
The present disclosure provides a technique capable of controlling a shape of an SAM. Provided is a method of forming a target film on a substrate, wherein the method includes preparing a substrate including a layer of a first conductive material formed on a surface of a first region, and a layer of an insulating material formed on a surface of a second region; forming carbon nanotubes on a surface of the layer of the first conductive material; and supplying a raw material gas for a self-assembled film to form the self-assembled film in a region of the surface of the layer of the first conductive material in which the carbon nanotubes have not been formed.
FILM-FORMING METHOD
The present disclosure provides a technique capable of controlling a shape of an SAM. Provided is a method of forming a target film on a substrate, wherein the method includes preparing a substrate including a layer of a first conductive material formed on a surface of a first region, and a layer of an insulating material formed on a surface of a second region; forming carbon nanotubes on a surface of the layer of the first conductive material; and supplying a raw material gas for a self-assembled film to form the self-assembled film in a region of the surface of the layer of the first conductive material in which the carbon nanotubes have not been formed.
Method of forming a device structure using selective deposition of gallium nitride and system for same
A method of forming a device structure including a selectively-deposited gallium nitride layer is disclosed.
Process and manufacture of low-dimensional materials supporting both self-thermalization and self-localization
Various articles and devices can be manufactured to take advantage of a what is believed to be a novel thermodynamic cycle in which spontaneity is due to an intrinsic entropy equilibration. The novel thermodynamic cycle exploits the quantum phase transition between quantum thermalization and quantum localization. Preferred devices include a phonovoltaic cell, a rectifier and a conductor for use in an integrated circuit.
Process and manufacture of low-dimensional materials supporting both self-thermalization and self-localization
Various articles and devices can be manufactured to take advantage of a what is believed to be a novel thermodynamic cycle in which spontaneity is due to an intrinsic entropy equilibration. The novel thermodynamic cycle exploits the quantum phase transition between quantum thermalization and quantum localization. Preferred devices include a phonovoltaic cell, a rectifier and a conductor for use in an integrated circuit.
JANUS TRANSITION METAL DICHALCOGENIDE THIN FILM AND METHOD OF FABRICATING THE SAME
Disclosed is a method of fabricating a Janus transition metal dichalcogenide thin film. More particularly, the method includes a first step of depositing a transition metal dichalcogenide thin film including a first chalcogen element on an oxide silicon substrate; a second step of a vacancy forming in the transition metal dichalcogenide thin film; and a third step of substituting the first chalcogen element with a second chalcogen element to form a Janus transition metal dichalcogenide thin film. The first step, the second step, and the third step may be performed in a single CVD process in a same reaction chamber.
Therefore, the present disclosure can shorten the processing time of a Janus transition metal dichalcogenide thin film and can reduce the manufacturing cost thereof. In addition, the present disclosure can minimize damage to the Janus transition metal dichalcogenide thin film during the fabrication process, thereby being capable of a high-quality single-crystal Janus transition metal dichalcogenide thin film.
Atomic layer deposition and etching of transition metal dichalcogenide thin films
Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH.sub.3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O.sub.2 as the etching reactant and an inert gas such as N.sub.2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.
METHODS TO REDUCE MATERIAL SURFACE ROUGHNESS
Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the silicon-containing precursor or the boron-containing precursor is greater than or about 1:1. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber.