A process for large-scale production of graphene comprising a step of applying graphene onto a movable surface carrying multiple particles using a PECVD-based process operating at low temperatures enabling the coating of materials that are at risk of melting, decomposing or deforming at higher temperatures. The graphene can be separated from said particles, and the particles re-circulated in the process. A production unit designed for continuous or semi-continuous large-scale production of graphene and graphene-coated particles, where said graphene-coated particles are either the desired end-product, or an intermediate. Graphene-coated particles, in particular particles where the graphene forms flakes having a desired orientation in relation to a surface of said particles.

A process for large-scale production of graphene comprising a step of applying graphene onto a movable surface carrying multiple particles using a PECVD-based process operating at low temperatures enabling the coating of materials that are at risk of melting, decomposing or deforming at higher temperatures. The graphene can be separated from said particles, and the particles re-circulated in the process. A production unit designed for continuous or semi-continuous large-scale production of graphene and graphene-coated particles, where said graphene-coated particles are either the desired end-product, or an intermediate. Graphene-coated particles, in particular particles where the graphene forms flakes having a desired orientation in relation to a surface of said particles.

A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.

An apparatus for processing a substrate is provided. The apparatus comprises a processing chamber and a showerhead. The showerhead is in the processing chamber and has a plurality of first holes with a first size in a first zone of the showerhead, a plurality of second holes with a second hole size in a second zone of the showerhead, and a plurality of third holes with a third hole size in a third zone of the showerhead. The first hole size is different from the second hole size. The first zone is surrounded by the second zone. An area of the first zone is larger than an area of the second zone. The first hole size is different from the third hole size. The first zone is surrounded by the third zone, and an area of the first zone is larger than an area of the third zone.

Provided is a mist generator including: a container that stores a liquid; a gas supply unit that supplies a gas into the container; and an electrode that generates plasma of the gas between the electrode and the liquid, where the supply direction of the gas fed from the gas supply opening of the gas supply unit is different from a direction in which gravity acts.

Provided is a mist generator including: a container that stores a liquid; a gas supply unit that supplies a gas into the container; and an electrode that generates plasma of the gas between the electrode and the liquid, where the supply direction of the gas fed from the gas supply opening of the gas supply unit is different from a direction in which gravity acts.

The disclosure provides a metal surface layer treating method, a metal assembly and an electronic device. The metal surface layer treating method includes: putting metal into a vacuum chamber, and vacuumizing the vacuum chamber to a first vacuum degree; adding a mixed gas of acetylene, nitrogen and hydrogen into the vacuum chamber; and heating the vacuum chamber to a temperature above an ambient temperature. In response to the temperature in the vacuum chamber reaching a first temperature value above the ambient temperature and a gas pressure of the vacuum chamber reaching a first pressure value, performing glow discharge so that a carbon-nitrogen gradient hardening layer is formed on a surface layer of the metal. The method includes removing part of a carbon layer of the surface layer of the carbon-nitrogen gradient hardening layer.

The disclosure provides a metal surface layer treating method, a metal assembly and an electronic device. The metal surface layer treating method includes: putting metal into a vacuum chamber, and vacuumizing the vacuum chamber to a first vacuum degree; adding a mixed gas of acetylene, nitrogen and hydrogen into the vacuum chamber; and heating the vacuum chamber to a temperature above an ambient temperature. In response to the temperature in the vacuum chamber reaching a first temperature value above the ambient temperature and a gas pressure of the vacuum chamber reaching a first pressure value, performing glow discharge so that a carbon-nitrogen gradient hardening layer is formed on a surface layer of the metal. The method includes removing part of a carbon layer of the surface layer of the carbon-nitrogen gradient hardening layer.

Exemplary semiconductor processing methods to clean a substrate processing chamber are described. The methods may include depositing a dielectric film on a first substrate in a substrate processing chamber, where the dielectric film may include a silicon-carbon-oxide. The first substrate having the dielectric film may be removed from the substrate processing chamber, and the dielectric film may be deposited on at least one more substrate in the substrate processing chamber. The at least one more substrate may be removed from the substrate processing chamber after the dielectric film is deposited on the substrate. Etch plasma effluents may flow into the substrate processing chamber after the removal of a last substrate having the dielectric film. The etch plasma effluents may include greater than or about 500 sccm of NF.sub.3 plasma effluents, and greater than or about 1000 sccm of O.sub.2 plasma effluents.

Exemplary semiconductor processing methods to clean a substrate processing chamber are described. The methods may include depositing a dielectric film on a first substrate in a substrate processing chamber, where the dielectric film may include a silicon-carbon-oxide. The first substrate having the dielectric film may be removed from the substrate processing chamber, and the dielectric film may be deposited on at least one more substrate in the substrate processing chamber. The at least one more substrate may be removed from the substrate processing chamber after the dielectric film is deposited on the substrate. Etch plasma effluents may flow into the substrate processing chamber after the removal of a last substrate having the dielectric film. The etch plasma effluents may include greater than or about 500 sccm of NF.sub.3 plasma effluents, and greater than or about 1000 sccm of O.sub.2 plasma effluents.