Provided is a sensor including a substrate that includes a major surface, a sensor part that includes a gas flow path formed of a porous material, and at least one of a heater or a temperature sensor. The heater is capable of heating the sensor part, the temperature sensor is capable of measuring temperature of the sensor part, the sensor part and the at least one of the heater or the temperature sensor are stacked over the major surface, the at least one of the heater or the temperature sensor is an interconnect having forward tapered side surfaces, and the at least one of the heater or the temperature sensor includes a metal interconnect layer, and the forward tapered side surfaces of the interconnect overlap with the gas flow path in plan view of the major surface.

Exemplary etching methods may include flowing a fluorine-containing precursor and a hydrogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The hydrogen-containing precursor may be flowed at a flow rate of at least 2:1 relative to the flow rate of the fluorine-containing precursor. The methods may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents into a substrate processing region housing a substrate. The substrate may include an exposed region of a tantalum or titanium material and an exposed region of a silicon-containing material or a metal. The methods may include contacting the substrate with the plasma effluents. The methods may include removing the tantalum or titanium material selectively to the silicon-containing material or the metal.

Exemplary etching methods may include flowing a fluorine-containing precursor and a hydrogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The hydrogen-containing precursor may be flowed at a flow rate of at least 2:1 relative to the flow rate of the fluorine-containing precursor. The methods may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents into a substrate processing region housing a substrate. The substrate may include an exposed region of a tantalum or titanium material and an exposed region of a silicon-containing material or a metal. The methods may include contacting the substrate with the plasma effluents. The methods may include removing the tantalum or titanium material selectively to the silicon-containing material or the metal.

Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

Provided is a plasma etching method which enables etching with high accuracy while controlling and reducing surface roughness of a transition metal film. The etching is performed for the transition metal film, which is formed on a sample and contains a transition metal element, by a first step of isotropically generating a layer of transition metal oxide on a surface of the transition metal film while a temperature of the sample is maintained at 100° C. or lower, a second step of raising the temperature of the sample to a predetermined temperature of 150° C. or higher and 250° C. or lower while a complexation gas is supplied to the layer of transition metal oxide, a third step of subliming and removing a reactant generated by an reaction between the complexation gas and the transition metal oxide formed in the first step while the temperature of the sample is maintained at 150° C. or higher and 250° C. or lower, and a fourth step of cooling the sample.

The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.