The present invention provides a plating method capable of easily performing various decorative plating processes. The plating method includes a bulge forming process of forming a bulge on an object to be plated by ejecting ink drops of first UV-curable ink from an inkjet head such that the ejected ink drops land on the object, and a plating process of plating the object having the bulge formed thereon, after the bulge forming process. Also, in the bulge forming process, the bulge is formed such that a second surface of the bulge to be plated has surface roughness different from that of a first surface of the object to be plated.

Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.

A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

Method and apparatus are provided for electroplating a surface area of an internal wall defining a cooling cavity present in a gas turbine engine component.

A process to form devices may include forming a seed layer on and/or over a substrate, modifying a seed layer selectively, forming an image-wise mold layer on and/or over a substrate and/or electrodepositing a first material on and/or over an exposed conductive area. A process may include selectively applying a temporary patterned passivation layer on a conductive substrate, selectively forming an image-wise mold layer on and/or over a substrate, forming a first material on and/or over at least one of the exposed conductive areas and/or removing a temporary patterned passivation layer. A process may include forming a sacrificial image-wise mold layer on a substrate layer, selectively placing one or more first materials in one or more exposed portions of a substrate layer, forming one or more second materials on and/or over a substrate layer and/or removing a portion of a sacrificial image-wise mold layer.

A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions. When the panel-shaped metal wall grids array is used for panel level IC packaging, at least one IC chip/IC die is disposed in each metal wall grid with a top surface of each IC chip/IC die facing downwards, and a panel-shaped metal layer matching with the panel-shaped wall grids array may be further formed on the entire back side of the panel-shaped metal wall grids array so that the panel-shaped metal layer is bonded to the metal wall of each metal wall grid.

Sequential electrodeposition of metals into through-mask features on a semiconductor substrate is conducted such as to reduce the deleterious consequences of lipseal's pressure onto the mask material. In a first electroplating step, a first metal (e.g., nickel) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a first distance from the edge of the substrate. In a second electroplating step, a second metal (e.g., tin) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a greater distance from the edge of the substrate than the first distance. This allows to at least partially shift the lipseal pressure from a point that could have been damaged during the first electrodeposition step and to shield from electrolyte any cracks that might have formed in the mask material during the first electroplating step.

A method of producing layered cores for magnetic circuit components such as inductors and transformers suitable for use in the microelectronics industry. A series of pillars are created on a carrier Layers of the magnetic core are plated onto the exposed surface of the pillars. After the desired number of core layers are plated, the plated layers are ground down to expose the pillars, leaving a series of magnetic cores between the pillars. The pillars can then be removed, leaving a series of magnetic cores. The pillars are created by either building up pillars, such as copper pillars, or by slitting plastic mediums, such as dry film or epoxy plastic, the roughness of the magnetic cores produced depends on the method of forming the pillars.

An apparatus includes a template-former, a growth template, having a surface area containing three-dimensional features; a container which includes or retains electrolytes or other fluids from which materials are deposited, removed, or modified onto the growth template or to a structure-in-production; and a computer to plan and control said deposition, removal, or modification.

Iridium electroplating compositions containing 1,10-phenanthroline compounds in trace amounts to electroplate substantially defect-free uniform and smooth surface morphology indium on metal layers. The indium electroplating compositions can be used to electroplate indium metal on metal layers of various substrates such as semiconductor wafers and as thermal interface materials.