A valid portion formed on a mask sheet includes a first region and a second region. The first region is provided for each active region of a vapor deposited substrate, and has a shape corresponding to a shape of each active region. The second region is located outside the first region, and is provided with a covering portion configured to cover a plurality of vapor deposition holes.

A valid portion formed on a mask sheet includes a first region and a second region. The first region is provided for each active region of a vapor deposited substrate, and has a shape corresponding to a shape of each active region. The second region is located outside the first region, and is provided with a covering portion configured to cover a plurality of vapor deposition holes.

A fabrication method comprising: forming a mask of an amorphous material over a crystalline surface of a substrate, the mask having a pattern of openings defining areas of an active region in which one or more components of one or more active devices are to be formed, the mask further defining a non-active region in which no active devices are to be formed; and forming a deposition material through the mask by an epitaxial growth process. The deposition material thus forms in the openings of the active region. The pattern of openings through the mask further comprises one or more reservoirs formed in the non-active region, each of the reservoirs being connected by the pattern of openings in the mask to at least one of the areas in the active region, and the deposition material forming in the reservoirs as part of the epitaxial growth.

The present invention relates to a method for manufacturing a semiconductor material including a semi-polar III-nitride layer from a semi-polar starting substrate including a plurality of grooves periodically spaced apart, each groove including a first inclined flank of crystallographic orientation C (0001) and a second inclined flank of different crystallographic orientation, the method comprising the phases consisting in: forming (2) III-nitride crystals on the first inclined flanks of the grooves, the growth parameters of the III-nitride crystals being adapted to favor lateral growth of said crystals such as to induce overlapping between adjacent III-nitride crystals, and continuing growth until coalescence of the III-nitride crystals to form a layer of coalesced III-nitride crystals; forming (3) a two-dimensional III-nitride layer on the layer of coalesced III-nitride crystals.

The present invention relates to a method for manufacturing a semiconductor material including a semi-polar III-nitride layer from a semi-polar starting substrate including a plurality of grooves periodically spaced apart, each groove including a first inclined flank of crystallographic orientation C (0001) and a second inclined flank of different crystallographic orientation, the method comprising the phases consisting in: forming (2) III-nitride crystals on the first inclined flanks of the grooves, the growth parameters of the III-nitride crystals being adapted to favor lateral growth of said crystals such as to induce overlapping between adjacent III-nitride crystals, and continuing growth until coalescence of the III-nitride crystals to form a layer of coalesced III-nitride crystals; forming (3) a two-dimensional III-nitride layer on the layer of coalesced III-nitride crystals.

The present disclosure relates to a device and method for forming efficient quantum devices, in particular quantum devices that have not been contaminated in ex-situ processes. In particular the presently disclosed method can be applied for manufacturing of a Josephson junction which is an element in a tunable superconducting qubit. One embodiment relates to a method for in-situ production of a barrier/gap in the surface layer(s) of an elongated nanostructure, the method comprising the steps of providing at least one elongated device nanostructure on a substrate in a vacuum chamber having at least one deposition source, providing at least one elongated shadow nanostructure in said vacuum chamber, and depositing at least a first facet layer on at least a part of the device nanostructure(s) and the shadow nanostructure(s) by means of said deposition source, wherein the deposition source, the device nanostructure and the shadow nanostructure during deposition are arranged such that the shadow nanostructure covers and forms a shadow mask on at least a part of the device nanostructure thereby forming a gap in the first facet layer deposited on the device nanostructure.

The present disclosure relates to a device and method for forming efficient quantum devices, in particular quantum devices that have not been contaminated in ex-situ processes. In particular the presently disclosed method can be applied for manufacturing of a Josephson junction which is an element in a tunable superconducting qubit. One embodiment relates to a method for in-situ production of a barrier/gap in the surface layer(s) of an elongated nanostructure, the method comprising the steps of providing at least one elongated device nanostructure on a substrate in a vacuum chamber having at least one deposition source, providing at least one elongated shadow nanostructure in said vacuum chamber, and depositing at least a first facet layer on at least a part of the device nanostructure(s) and the shadow nanostructure(s) by means of said deposition source, wherein the deposition source, the device nanostructure and the shadow nanostructure during deposition are arranged such that the shadow nanostructure covers and forms a shadow mask on at least a part of the device nanostructure thereby forming a gap in the first facet layer deposited on the device nanostructure.

The present invention relates to a heterojunction semiconductor substrate having excellent dielectric properties, a method of manufacturing the same, and an electronic device using the same. The present invention provides a heterojunction semiconductor substrate with improved interlayer adhesion, low leakage current, and excellent dielectric properties that maintain strength in a ferroelectric fatigue experiment by interposing a metal layer and a conductive metal oxide layer on a semiconductor substrate to form an epitaxial oxide thin film layer composed of perovskite piezoelectric oxide. The heterojunction semiconductor substrate can be applied to sensors, actuators, transducers, or MEMS devices that use the high functionality of the high-quality epitaxial oxide thin film layer, including applications in electronic and optical devices.

The present invention relates to a heterojunction semiconductor substrate having excellent dielectric properties, a method of manufacturing the same, and an electronic device using the same. The present invention provides a heterojunction semiconductor substrate with improved interlayer adhesion, low leakage current, and excellent dielectric properties that maintain strength in a ferroelectric fatigue experiment by interposing a metal layer and a conductive metal oxide layer on a semiconductor substrate to form an epitaxial oxide thin film layer composed of perovskite piezoelectric oxide. The heterojunction semiconductor substrate can be applied to sensors, actuators, transducers, or MEMS devices that use the high functionality of the high-quality epitaxial oxide thin film layer, including applications in electronic and optical devices.

Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.