A base substrate includes a supporting substrate comprising aluminum oxide, and a base crystal layer provided on a main face of the supporting substrate, comprising a crystal of a nitride of a group 13 element and having a crystal growth surface. At lease one of a metal of a group 13 element and a reaction product of a material of the supporting substrate and the crystal of the nitride of the group 13 element is present between the raised part and the supporting substrate. The reaction product contains at least aluminum and a group 13 element.

A method for manufacturing a semiconductor wafer according to the invention of the present application includes a first step of forming a gallium nitride growth layer which is divided into a plurality of small sections, on an upper surface of a silicon substrate and a second step of filling portions between the plurality of small sections with an insulating film, wherein the insulating film exerts stress to the silicon substrate in a direction opposite to a direction in which the gallium nitride growth layer exerts stress on the silicon substrate.

A method for manufacturing a semiconductor wafer according to the invention of the present application includes a first step of forming a gallium nitride growth layer which is divided into a plurality of small sections, on an upper surface of a silicon substrate and a second step of filling portions between the plurality of small sections with an insulating film, wherein the insulating film exerts stress to the silicon substrate in a direction opposite to a direction in which the gallium nitride growth layer exerts stress on the silicon substrate.

A deposition mask in which deformation of long sides is restrained is manufactured. A manufacturing method of a deposition mask includes a step of preparing a metal plate; a processing step of processing the metal plate into an intermediate product comprising: a plurality of deposition mask portions each including a pair of long sides and a pair of short sides, and having a plurality of through-holes formed therein; and a support portion that surrounds the plurality of deposition mask portions, and is partially connected to the short sides of the plurality of deposition mask portions; and a separation step of separating the deposition mask portions from the support portion to obtain the deposition mask. In the intermediate product, the long sides of the deposition mask portions are not connected to the support portion.

A deposition mask in which deformation of long sides is restrained is manufactured. A manufacturing method of a deposition mask includes a step of preparing a metal plate; a processing step of processing the metal plate into an intermediate product comprising: a plurality of deposition mask portions each including a pair of long sides and a pair of short sides, and having a plurality of through-holes formed therein; and a support portion that surrounds the plurality of deposition mask portions, and is partially connected to the short sides of the plurality of deposition mask portions; and a separation step of separating the deposition mask portions from the support portion to obtain the deposition mask. In the intermediate product, the long sides of the deposition mask portions are not connected to the support portion.

A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer (101) and a buffer layer (102), of a buffer material different from a material of the wafer, the buffer layer having a growth surface (1021); an array of nano structures (1010) epitaxially grown from the growth surface; a continuous planar layer (1020) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer (1030), epitaxially grown on the planar layer (1020).

A method of making a semiconductor device includes depositing an amorphous layer on a substrate, masking a portion of the amorphous layer, removing a portion of the amorphous layer to form a first channel into the amorphous layer, depositing a semiconductor layer onto the substrate layer, and removing at least a portion of a defect region of the semiconductor layer to form a second channel.

The disclosure is aimed at a method for obtaining non-polar III-Nitride compact layers by coalescence of an ordered-array of etched non-polar 111-Nitride nanopillars. Besides, the disclosure also relates to the non-polar III-Nitride binary and ternary compact, continuous (2D) films, layers, or pseudo-substrates, obtainable by means of the disclosed method and having advantageous properties. The disclosure also includes a specific group of non-polar III-Nitride compact, continuous (2D) films or layers, having one of the components selected from the group consisting of In, Al and both elements, enfolding ordered arrays of non-polar III-Nitride nano-crystals, regardless the method for obtaining thereof, said film or layer being one of the groups consisting of: non-polar InN, non-polar AlN, non-polar Ga.sub.xAl.sub.1-xN, non-polar In.sub.xAl.sub.1-xN and non-polar GaxIn.sub.1-xN, where 0<x<1.

Provided is a laminated structure that has a crystalline film having a large area, which is useful for a semiconductor device, etc., and having a good film thickness distribution in which the film thickness is 30 μm or less, and that has excellent heat dissipation. In a laminated structure in which a crystal film containing a crystalline metal oxide as a main component is laminated on a support directly or with another layer therebetween, the support has a thermal conductivity of 100 W/m.Math.K or more at room temperature, and the crystal film has a corundum structure. Furthermore, the film thickness of the crystal film is 1 μm to 30 μm, the area of the crystal film is 15 cm.sup.2 or more, the distribution of the film thickness in the area is in the range of ±10% or less.

A nanowire structure includes a substrate, a patterned mask layer, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. Further, the patterned mask layer has a thermal conductivity greater than $20\frac{W}{m*K}.$
The nanowire is on the substrate in the opening of the patterned mask layer. By providing the patterned mask layer with a thermal conductivity greater than $20\frac{W}{m*K},$
the patterned mask layer is able to maintain a temperature of the surface thereof to a desired level when the nanowire is provided. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.