This application relates to the electronic technology application field and provides a silicon-based substrate (10), a substrate, a manufacturing method thereof, and an optoelectronic device. The substrate includes: the silicon-based substrate (10), where one surface of the silicon-based substrate (10) has periodic protrusion structures (101), and there is an angle of inclination between a side face of each protrusion structure (101) and a bottom surface; and a group III-V material layer (20) disposed on the surface that is of the silicon-based substrate (10) and that has the protrusion structures (101).

A nanowire structure includes a substrate, a patterned mask layer, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. Further, the patterned mask layer has a thermal conductivity greater than

[00001]$20\frac{W}{m*K}.$

The nanowire is on the substrate in the opening of the patterned mask layer. By providing the patterned mask layer with a thermal conductivity greater than

[00002]$20\frac{W}{m*K},$

the patterned mask layer is able to maintain a temperature of the surface thereof to a desired level when the nanowire is provided. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.

According to one embodiment, a crystal growth method includes forming a first member at at least a part of a bottom portion of a hole in a structure body. The hole includes the bottom portion and a side portion. The first member includes a first element. The first element is not adhered to at least a part of the side portion in the forming the first member. The crystal growth method includes growing a crystal member inside the hole by supplying a source material to the hole after the forming the first member. The source material includes a second element. The crystal member includes the second element.

Disclosed are a mask plate and an assembly method thereof. The mask plate includes a covering bar; a support bar; and at least one mask sheet, the mask sheet includes one mask area, a mask pattern is distributed in the entire mask area; and the covering bar and the support bar are intersected with each other to divide the mask area into a plurality of mask units. Thus, the mask sheet will not produce wrinkle in different degrees upon being stretched, in this way, the accuracy of the deposited or evaporated pattern can be improved, and the yield of the mask plate can be improved as well.

A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.

A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.

A SiC wafer defect measuring method which includes a device management step of managing a defect measuring device by irradiating a reference sample made of a material having a light-emitting intensity that does not change with repeated irradiation by excitation light and which has a pattern made of recesses and/or protrusions in the surface, the irradiation by the excitation light being performed before measuring defects in a SiC wafer and under the same irradiation conditions as the measurement of the defects in the SiC wafer, and then measuring the S/N ratio of the pattern from a reflection image of the pattern.

A SiC wafer defect measuring method which includes a device management step of managing a defect measuring device by irradiating a reference sample made of a material having a light-emitting intensity that does not change with repeated irradiation by excitation light and which has a pattern made of recesses and/or protrusions in the surface, the irradiation by the excitation light being performed before measuring defects in a SiC wafer and under the same irradiation conditions as the measurement of the defects in the SiC wafer, and then measuring the S/N ratio of the pattern from a reflection image of the pattern.