A method of making a semiconductor device includes depositing an amorphous layer on a substrate, masking a portion of the amorphous layer, removing a portion of the amorphous layer to form a first channel into the amorphous layer, depositing a semiconductor layer onto the substrate layer, and removing at least a portion of a defect region of the semiconductor layer to form a second channel.

A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.

A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.

A method of manufacturing a semiconductor device, including: forming a membrane forming pattern on a substrate; forming a membrane material layer on the substrate, wherein the membrane material layer covers the membrane forming pattern; forming a membrane having a protruding pattern by crystallizing the membrane material layer; forming a two-dimensional (2D) material pattern on the protruding pattern by growing a 2D material on the membrane; and transferring the 2D material pattern to a transfer substrate

A method of manufacturing a semiconductor device, including: forming a membrane forming pattern on a substrate; forming a membrane material layer on the substrate, wherein the membrane material layer covers the membrane forming pattern; forming a membrane having a protruding pattern by crystallizing the membrane material layer; forming a two-dimensional (2D) material pattern on the protruding pattern by growing a 2D material on the membrane; and transferring the 2D material pattern to a transfer substrate

A deposition mask in which deformation of long sides is restrained is manufactured. A manufacturing method of a deposition mask includes a step of preparing a metal plate; a processing step of processing the metal plate into an intermediate product comprising: a plurality of deposition mask portions each including a pair of long sides and a pair of short sides, and having a plurality of through-holes formed therein; and a support portion that surrounds the plurality of deposition mask portions, and is partially connected to the short sides of the plurality of deposition mask portions; and a separation step of separating the deposition mask portions from the support portion to obtain the deposition mask. In the intermediate product, the long sides of the deposition mask portions are not connected to the support portion.

The disclosure relates to large area single crystal diamond (SCD) surfaces and substrates, and their methods of formation. Typical large area substrates can be at least about 25 mm, 50 mm, or 100 mm in diameter or square edge length, and suitable thicknesses can be about 100 m to 1000 m. The large area substrates have a high degree of crystallographic alignment. The large area substrates can be used in a variety of electronics and/or optics applications. Methods of forming the large area substrates generally include lateral and vertical growth of SCD on spaced apart and crystallographically aligned SCD seed substrates, with the individual SCD growth layers eventually merging to form a composite SCD layer of high quality and high crystallographic alignment. A diamond substrate holder can be used to crystallographically align the SCD seed substrates and reduce the effect of thermal stress on the formed SCD layers.

The disclosure relates to large area single crystal diamond (SCD) surfaces and substrates, and their methods of formation. Typical large area substrates can be at least about 25 mm, 50 mm, or 100 mm in diameter or square edge length, and suitable thicknesses can be about 100 m to 1000 m. The large area substrates have a high degree of crystallographic alignment. The large area substrates can be used in a variety of electronics and/or optics applications. Methods of forming the large area substrates generally include lateral and vertical growth of SCD on spaced apart and crystallographically aligned SCD seed substrates, with the individual SCD growth layers eventually merging to form a composite SCD layer of high quality and high crystallographic alignment. A diamond substrate holder can be used to crystallographically align the SCD seed substrates and reduce the effect of thermal stress on the formed SCD layers.

A manufacturing method allows growth of a group III nitride semiconductor layer on a Si substrate with an AlN buffer layer interposed between same, so as to suppress group III material from diffusing into the Si substrate. The group III nitride semiconductor substrate manufacturing method includes: a step of forming an AlN coating on the inside of a furnace; steps of installing an Si substrate in the furnace covered with the AlN coating and forming an AlN buffer layer on the Si substrate; and a step of forming a group III nitride semiconductor layer on the AN buffer layer.

A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.