According to one embodiment, a scintillator includes a first layer provided on a surface of a substrate and including thallium activated cesium iodide; and a second layer provided on the first layer and including thallium activated cesium iodide. The second layer includes crystals having a [100] orientation partially diverted from a direction perpendicular to the surface of the substrate. Half width at half maximum of a frequency distribution curve of an angle between the direction perpendicular to the surface of the substrate and the [001] orientation, which is obtained by measuring the angle using EBSD method, is 2.4 degree or less.

A silicon single crystal substrate for vapor phase growth, having the silicon single crystal substrate being made of an FZ crystal having a resistivity of 1000 Ωcm or more, wherein the surface of the silicon single crystal substrate is provided with a high nitrogen concentration layer having a nitrogen concentration higher than that of other regions and a nitrogen concentration of 5×10.sup.15 atoms/cm.sup.3 or more and a thickness of 10 to 100 μm.

A method for washing an aluminum nitride single crystal substrate, the aluminum nitride single crystal substrate including: an aluminum-polar face; and a nitrogen-polar face opposite to the aluminum-polar face, the method including: (a) scrubbing a surface of the nitrogen-polar face.

In a general aspect, a ceramic thin film with nanotwinned regions at a tunable volume fraction is manufactured. In some aspects, a method for manufacturing a ceramic thin film on a surface of a substrate in an evacuated chamber is disclosed. The ceramic thin film includes crystalline grains; and each of the crystalline grains includes one or more nanotwinned regions. The one or more nanotwinned regions have a volume fraction in a range of 30-80% of the ceramic thin film. The ceramic thin film comprises titanium, nitrogen, and boron. A plurality of targets including a plurality of sputtering materials is prepared. A gas atmosphere in the evacuated chamber is formed. Electric power is supplied to the plurality of targets to cause co-sputtering of the plurality of sputtering materials to form the ceramic thin film with the one or more nanotwinned regions.

In a general aspect, a ceramic thin film with nanotwinned regions at a tunable volume fraction is manufactured. In some aspects, a method for manufacturing a ceramic thin film on a surface of a substrate in an evacuated chamber is disclosed. The ceramic thin film includes crystalline grains; and each of the crystalline grains includes one or more nanotwinned regions. The one or more nanotwinned regions have a volume fraction in a range of 30-80% of the ceramic thin film. The ceramic thin film comprises titanium, nitrogen, and boron. A plurality of targets including a plurality of sputtering materials is prepared. A gas atmosphere in the evacuated chamber is formed. Electric power is supplied to the plurality of targets to cause co-sputtering of the plurality of sputtering materials to form the ceramic thin film with the one or more nanotwinned regions.

Embodiments of the present invention generally relate to methods of epitaxially growing boron-containing structures. In an embodiment, a method of depositing a structure comprising boron and a Group IV element on a substrate is provided. The method includes heating the substrate at a temperature of about 300° C. or more within a chamber, the substrate having a dielectric material and a single crystal formed thereon. The method further includes flowing a first process gas and a second process gas into the chamber, wherein: the first process gas comprises at least one boron-containing gas comprising a haloborane; and the second process gas comprises at least one Group IV element-containing gas. The method further includes exposing the substrate to the first and second process gases to epitaxially and selectively deposit the structure comprising boron and the Group IV element on the single crystal.

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing plurality of substrates to a process chamber. A plurality of deposition cycles are executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial comprises a plurality of epitaxial pairs, each pair comprising a first epitaxial layer and a second epitaxial layer. The deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer and the second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer

A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.