Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

A nanowire structure includes a substrate, a patterned mask layer, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. Further, the patterned mask layer has a thermal conductivity greater than $20\frac{W}{m*K}.$
The nanowire is on the substrate in the opening of the patterned mask layer. By providing the patterned mask layer with a thermal conductivity greater than $20\frac{W}{m*K},$
the patterned mask layer is able to maintain a temperature of the surface thereof to a desired level when the nanowire is provided. This prevents undesired parasitic growth on the patterned mask layer, thereby improving the performance of the nanowire structure.

A method for fabricating porous wire-in-tube (WiT) nanostructures including forming a first porous core-shell nanostructure, forming a second porous core-shell nanostructure by increasing thickness and porosity of the porous core-shell nanostructure, and forming a porous WiT nanostructure by etching the second porous core-shell nanostructure. Forming the first porous core-shell nanostructure may include forming a porous layer on a semi-conductive core by depositing a first plurality of particles on the semi-conductive core and generating an initial porous semi-conductive core by etching the semi-conductive core simultaneously with forming the porous layer.

A monocrystalline germanium wafer that increases the open-circuit voltage of multijunction solar cells, a method for preparing the monocrystalline germanium wafer and a method for preparing an ingot from which the monocrystalline germanium wafer is prepared. The monocrystalline germanium wafer that increases the open-circuit voltage of the bottom cell of multijunction solar cells is prepared by adjusting the amounts of the co-dopants silicon and gallium in the monocrystalline germanium wafer, the ratio of silicon to gallium in the preparation of the monocrystalline germanium.

A monocrystalline germanium wafer that increases the open-circuit voltage of multijunction solar cells, a method for preparing the monocrystalline germanium wafer and a method for preparing an ingot from which the monocrystalline germanium wafer is prepared. The monocrystalline germanium wafer that increases the open-circuit voltage of the bottom cell of multijunction solar cells is prepared by adjusting the amounts of the co-dopants silicon and gallium in the monocrystalline germanium wafer, the ratio of silicon to gallium in the preparation of the monocrystalline germanium.