A method of growing a crystal in a recess in a substrate on which an insulating film having the recess is formed, includes: forming a first film on the insulating film at a thickness as not to completely fill the recess; etching the first film by an etching gas to remain the first film only in a bottom portion of the recess; annealing the substrate such that the first film in the bottom portion is modified into a crystalline layer; forming a second film on the insulating film and a surface of the crystalline layer at a thickness as not to completely fill the recess; annealing the substrate such that the second film is crystallized from the bottom portion through a solid phase epitaxial growth to form an epitaxial crystal layer; and etching and removing the second film remaining on the substrate by an etching gas.

There is described a method of manufacturing a substrate for an optoelectronic device. The method has the steps of: supporting a first layer of a first crystalline material on a second layer of a second crystalline material different from said first crystalline material thereby exposing crystalline defects at a surface of said first layer; etching said first layer using first etching conditions, at least some of said crystalline defects expanding into pores running from said surface of the first layer towards said second layer; and heating said first and second layers up to a first temperature for a first period of time within a given environment, said heating transforming said pores into nanovoids attracting at least some of said crystalline defects away from said surface. In some embodiments, the method has a step of reheating the layers or a step of forming a pore containing region within the first layer.

There is described a method of manufacturing a substrate for an optoelectronic device. The method has the steps of: supporting a first layer of a first crystalline material on a second layer of a second crystalline material different from said first crystalline material thereby exposing crystalline defects at a surface of said first layer; etching said first layer using first etching conditions, at least some of said crystalline defects expanding into pores running from said surface of the first layer towards said second layer; and heating said first and second layers up to a first temperature for a first period of time within a given environment, said heating transforming said pores into nanovoids attracting at least some of said crystalline defects away from said surface. In some embodiments, the method has a step of reheating the layers or a step of forming a pore containing region within the first layer.

Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

An engineered substrate includes a support structure comprising a polycrystalline ceramic core, an adhesion layer coupled to the polycrystalline ceramic core, and a barrier layer coupled to the adhesion layer. The engineered substrate also includes an bonding layer coupled to the support structure, a substantially single crystal layer coupled to the bonding layer, and an epitaxial gallium nitride layer coupled to the substantially single crystal layer.

An engineered substrate includes a support structure comprising a polycrystalline ceramic core, an adhesion layer coupled to the polycrystalline ceramic core, and a barrier layer coupled to the adhesion layer. The engineered substrate also includes an bonding layer coupled to the support structure, a substantially single crystal layer coupled to the bonding layer, and an epitaxial gallium nitride layer coupled to the substantially single crystal layer.

The process for manufacturing a product (1) including nanoelements (2) includes: forming (E2) a mixture (6) including a plurality of electrically conductive grains (3), a catalyst (4) separate from the grains (3) of the electrically conductive grains, and a reactant (7) that is liquid or in the form of a suspension of solid particles in a liquid solvent and comprises a precursor of the material intended to form the nanoelements (2); introducing the mixture (6) into a chamber of a reactor and pressurizing the reactor to a pressure less than or equal to 1 bar; and obtaining (E3) the product (1) from the mixture (6) comprising a step (E3-1) of growing the nanoelements (2) from the catalyst (4), then combined with the grains (3) of the electrically conductive grains, the growth step (E3-1) being carried out by a step of heat treatment applied to the mixture (6).