Patent classifications
C30B29/38
Semiconductor substrate, gallium nitride single crystal, and method for producing gallium nitride single crystal
There is provided a semiconductor substrate including: a sapphire substrate; an intermediate layer formed of gallium nitride with random crystal directions and provided on the sapphire substrate; and at least one or more semiconductor layers each of which is formed of a gallium nitride single crystal and that are provided on the intermediate layer.
Semiconductor substrate, gallium nitride single crystal, and method for producing gallium nitride single crystal
There is provided a semiconductor substrate including: a sapphire substrate; an intermediate layer formed of gallium nitride with random crystal directions and provided on the sapphire substrate; and at least one or more semiconductor layers each of which is formed of a gallium nitride single crystal and that are provided on the intermediate layer.
COMPOSITE STRUCTURE OF CERAMIC SUBSTRATE
A composite structure of a ceramic substrate, including a first ceramic substrate formed by crystal growth, which has a first surface and a second surface opposite to each other, and has only vertical via holes filled with conductive material, so that the first surface and the second surface of the first ceramic substrate are electrically connected; and a thin film substrate disposed on the second surface of the first ceramic substrate, and one of the surfaces is electrically connected to the second surface of the first ceramic substrate, and an electrical connection point is provided on the other surface of the thin film substrate to electrically connect an external element or another circuit board.
COMPOSITE STRUCTURE OF CERAMIC SUBSTRATE
A composite structure of a ceramic substrate, including a first ceramic substrate formed by crystal growth, which has a first surface and a second surface opposite to each other, and has only vertical via holes filled with conductive material, so that the first surface and the second surface of the first ceramic substrate are electrically connected; and a thin film substrate disposed on the second surface of the first ceramic substrate, and one of the surfaces is electrically connected to the second surface of the first ceramic substrate, and an electrical connection point is provided on the other surface of the thin film substrate to electrically connect an external element or another circuit board.
Pressure container for crystal production
A pressure container for crystal production having excellent corrosion-resistance is provided. This pressure container produces crystals within the container using a seed crystal, a mineralizer, a raw material, and ammonia in a supercritical state or a subcritical state as a solvent. The pressure container has Ag present over the entire surface of at least the inner surface thereof in contact with the solvent. The Ag can be disposed by one or a combination of two or more among, for instance, Ag lining, Ag welding, and Ag plating. The mineralizer is preferably a fluorine mineralizer containing no halogen atoms other than fluorine.
Pressure container for crystal production
A pressure container for crystal production having excellent corrosion-resistance is provided. This pressure container produces crystals within the container using a seed crystal, a mineralizer, a raw material, and ammonia in a supercritical state or a subcritical state as a solvent. The pressure container has Ag present over the entire surface of at least the inner surface thereof in contact with the solvent. The Ag can be disposed by one or a combination of two or more among, for instance, Ag lining, Ag welding, and Ag plating. The mineralizer is preferably a fluorine mineralizer containing no halogen atoms other than fluorine.
Crystal laminate, semiconductor device and method for manufacturing the same
Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula In.sub.xAl.sub.yGa.sub.1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm.sup.−1 or more and 4.6 cm.sup.−1 or less under a temperature condition of normal temperature.
Crystal laminate, semiconductor device and method for manufacturing the same
Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula In.sub.xAl.sub.yGa.sub.1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm.sup.−1 or more and 4.6 cm.sup.−1 or less under a temperature condition of normal temperature.
Low Temperature Plasma-Assisted Atomic Layer Epitaxy of Hexagonal InN Films and its Alloys with AlN
Described herein is a method for growing indium nitride (InN) materials by growing hexagonal InN using a pulsed growth method at a temperature lower than 300° C.
Conductive C-plane GaN substrate
A conductive C-plane GaN substrate has a resistivity of 2×10.sup.−2 Ω.Math.cm or less or an n-type carrier concentration of 1×10.sup.18 cm.sup.−3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.