A method for clonal-growth of a single-crystal metal, including: using copper as an example, placing an existing small-sized single-crystal copper foil with a plane of any index on a copper foil that needs to be single-crystallized, and performing annealing to obtain, by cloning, a large-area (in meters) single-crystal copper foil with the same surface index as that of the parent facet. The method solves the difficult problem of large-area single-crystal copper foil preparation. By performing annealing, a parent single-crystal copper foil with a very small size (˜0.25 cm.sup.2) can be cloned to produce a large-area (˜700 cm.sup.2) single-crystal copper foil, which is an increase in area of about 3000 times.

A method for clonal-growth of a single-crystal metal, including: using copper as an example, placing an existing small-sized single-crystal copper foil with a plane of any index on a copper foil that needs to be single-crystallized, and performing annealing to obtain, by cloning, a large-area (in meters) single-crystal copper foil with the same surface index as that of the parent facet. The method solves the difficult problem of large-area single-crystal copper foil preparation. By performing annealing, a parent single-crystal copper foil with a very small size (˜0.25 cm.sup.2) can be cloned to produce a large-area (˜700 cm.sup.2) single-crystal copper foil, which is an increase in area of about 3000 times.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A synthetic diamond plate comprising a polygonal plate formed of synthetic diamond material, the polygonal plate of synthetic diamond material having a thickness in a range 0.4 mm to 1.5 mm, and rounded corners having a radius of curvature in a range 1 mm to 6 mm. A mounted synthetic diamond plate is also disclosed comprising a polygonal synthetic diamond plate as described and a base to which the polygonal synthetic diamond plate is bonded, wherein the base comprises a cooling channel. An array of mounted synthetic diamond plates is also described, comprising a plurality of mounted synthetic diamond plates described above, wherein the cooling channels of the mounted synthetic diamond plates are linked to form a common cooling channel across the array of mounted synthetic diamond plates.

A synthetic diamond plate comprising a polygonal plate formed of synthetic diamond material, the polygonal plate of synthetic diamond material having a thickness in a range 0.4 mm to 1.5 mm, and rounded corners having a radius of curvature in a range 1 mm to 6 mm. A mounted synthetic diamond plate is also disclosed comprising a polygonal synthetic diamond plate as described and a base to which the polygonal synthetic diamond plate is bonded, wherein the base comprises a cooling channel. An array of mounted synthetic diamond plates is also described, comprising a plurality of mounted synthetic diamond plates described above, wherein the cooling channels of the mounted synthetic diamond plates are linked to form a common cooling channel across the array of mounted synthetic diamond plates.

A method for preparing a large-size two-dimensional layered metal thiophosphate crystal includes the following steps: 1) weighing raw materials of indium spheres, phosphorous lumps and sulfur granules according to a predetermined amount and proportion, mixing them, and using iodine as a transport agent and potassium iodide as a molten salt; 2) adding the raw materials, the iodine and the potassium iodide to a reaction vessel together, and vacuum sealing it under a certain pressure, and then subjecting it to a high-temperature reaction; 3) taking out the products after the reaction, and washing the products to remove the residual iodine and potassium iodide and obtain large-size two-dimensional layered metal thiophosphate crystals. This method is simple and highly efficient.

A method for preparing a large-size two-dimensional layered metal thiophosphate crystal includes the following steps: 1) weighing raw materials of indium spheres, phosphorous lumps and sulfur granules according to a predetermined amount and proportion, mixing them, and using iodine as a transport agent and potassium iodide as a molten salt; 2) adding the raw materials, the iodine and the potassium iodide to a reaction vessel together, and vacuum sealing it under a certain pressure, and then subjecting it to a high-temperature reaction; 3) taking out the products after the reaction, and washing the products to remove the residual iodine and potassium iodide and obtain large-size two-dimensional layered metal thiophosphate crystals. This method is simple and highly efficient.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.