A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

In a case where a detector is positioned in a [11-20] direction, and where a first measurement region including a center of a main surface is irradiated with an X ray in a direction within ±15° relative to a [−1-120] direction, a ratio of a maximum intensity of a first intensity profile is more than or equal to 1500. In a case where the detector is positioned in a direction parallel to a [−1100] direction, and where the first measurement region is irradiated with an X ray in a direction within ±6° relative to a [1-100] direction, a ratio of a maximum intensity of a second intensity profile is more than or equal to 1500. An absolute value of a difference between maximum value and minimum value of energy at which the first intensity profile indicates a maximum value is less than or equal to 0.06 keV.

A method of manufacturing a hexagonal Group-III nitride semiconductor plate crystal using a crystal cutting wire. where the hexagonal semiconductor crystal has one principal face on one side and another principal face on an opposite side, and the hexagonal semiconductor crystal is cut by causing the crystal cutting wire to move so as to (i) divide the one principal face and the another principal face and (ii) satisfy conditions of Expressions (A) and (B):
25°<α≤90°  Expression (A); and
β=90°±5°  Expression (B) where α represents an angle formed by a c axis of the hexagonal Group-III nitride semiconductor crystal and a normal line of a crystal face cut out by the wire, and β represents an angle formed by a reference axis, which is obtained by perpendicularly projecting the c axis of the hexagonal Group-III nitride semiconductor crystal to the crystal face cut out by the wire, and a cutting direction.

A method of manufacturing a hexagonal Group-III nitride semiconductor plate crystal using a crystal cutting wire. where the hexagonal semiconductor crystal has one principal face on one side and another principal face on an opposite side, and the hexagonal semiconductor crystal is cut by causing the crystal cutting wire to move so as to (i) divide the one principal face and the another principal face and (ii) satisfy conditions of Expressions (A) and (B):
25°<α≤90°  Expression (A); and
β=90°±5°  Expression (B) where α represents an angle formed by a c axis of the hexagonal Group-III nitride semiconductor crystal and a normal line of a crystal face cut out by the wire, and β represents an angle formed by a reference axis, which is obtained by perpendicularly projecting the c axis of the hexagonal Group-III nitride semiconductor crystal to the crystal face cut out by the wire, and a cutting direction.

Nanostructures formed of metal nanostrands, and methods of forming the nanostrands, are described. These nanostructures can be used as a flexible or non-flexible, transparent or non-transparent conductive films or electronic circuit for various different applications. An example metal nanostrand can include: a first nanoplate joined laterally to a second nanoplate. Each of the nanoplates can have a top surface, a bottom surface and one or more side surfaces laterally extending from the top surface to the bottom surface. A (111) crystallographic plane can be arranged at each of the top surface and the bottom surface.

Embodiments described herein relate generally to the large scale production of functionalized graphene. In some embodiments, a method for producing functionalized graphene includes combining a crystalline graphite with a first electrolyte solution that includes at least one of a metal hydroxide salt, an oxidizer, and a surfactant. The crystalline graphite is then milled in the presence of the first electrolyte solution for a first time period to produce a thinned intermediate material. The thinned intermediate material is combined with a second electrolyte solution that includes a strong oxidizer and at least one of a metal hydroxide salt, a weak oxidizer, and a surfactant. The thinned intermediate material is then milled in the presence of the second electrolyte solution for a second time period to produce functionalized graphene.

Embodiments described herein relate generally to the large scale production of functionalized graphene. In some embodiments, a method for producing functionalized graphene includes combining a crystalline graphite with a first electrolyte solution that includes at least one of a metal hydroxide salt, an oxidizer, and a surfactant. The crystalline graphite is then milled in the presence of the first electrolyte solution for a first time period to produce a thinned intermediate material. The thinned intermediate material is combined with a second electrolyte solution that includes a strong oxidizer and at least one of a metal hydroxide salt, a weak oxidizer, and a surfactant. The thinned intermediate material is then milled in the presence of the second electrolyte solution for a second time period to produce functionalized graphene.

Proposed are a layered compound having indium and arsenic, a nanosheet that may be prepared using the same, and an electrical device including the materials. Proposed is a layered compound represented by [Formula 1] Na.sub.1-xIn.sub.yAs.sub.z (0≤x<1.0, 0.8≤y≤1.2, 1.2≤z≤1.8).

Disclosed herein are methods for exfoliation of single crystals allowing for growth of high crystalline quality on the exfoliated surfaces for III-V photovoltaics. Also disclosed herein are methods for growing GaAs (111) on layered-2D Bi.sub.2Se.sub.3 (0001) substrates in an MOCVD reactor.