C30B29/68

ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS
20220301855 · 2022-09-22 · ·

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS
20220301855 · 2022-09-22 · ·

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

Graphene and method for preparing same

The present disclosure relates to a method for preparing graphene, including: forming a dielectric material; and applying heat treatment concurrently with a gaseous carbon source on the dielectric material to grow.

Silicon carbide epitaxial wafer

A silicon carbide epitaxial wafer includes a single crystal silicon carbide substrate of 4H polytype having a major surface thereof inclined at an angle θ to a {0001} plane toward a <11-20> direction, and a silicon carbide epitaxial layer of a thickness t formed on the major surface, wherein a diameter of the single crystal silicon carbide substrate is greater than or equal to 150 mm, wherein the angle θ exceeds 0°, and is less than or equal to 6°, wherein one or more pairs of a screw dislocation pit and a diagonal line defect situated at a distance of t/tanθ from the pit are present in a surface of the silicon carbide epitaxial layer, and wherein a density of the pairs of a pit and a diagonal line defect is less than or equal to 2 pairs/cm2.

Silicon carbide epitaxial wafer

A silicon carbide epitaxial wafer includes a single crystal silicon carbide substrate of 4H polytype having a major surface thereof inclined at an angle θ to a {0001} plane toward a <11-20> direction, and a silicon carbide epitaxial layer of a thickness t formed on the major surface, wherein a diameter of the single crystal silicon carbide substrate is greater than or equal to 150 mm, wherein the angle θ exceeds 0°, and is less than or equal to 6°, wherein one or more pairs of a screw dislocation pit and a diagonal line defect situated at a distance of t/tanθ from the pit are present in a surface of the silicon carbide epitaxial layer, and wherein a density of the pairs of a pit and a diagonal line defect is less than or equal to 2 pairs/cm2.

NEAR-INFRARED LIGHT EMITTING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME

Provided are: a near infrared light-emitting semiconductor element that does not contain any harmful elements and that makes it possible to obtain near infrared light of a stable wavelength in a narrow band regardless of the operating environment; and a method for producing the near infrared light-emitting semiconductor element. GaN is used in the method for producing a near infrared light-emitting semiconductor element, and an active layer added in order to substitute Tm with Ga is formed on GaN in a reaction container at a growth rate of 0.1-30 μm/h without removal from said reaction container using an organometallic vapor phase growth method under temperature conditions of 600-1400° C. in a series of formation steps including formation of a p-type layer and an n-type layer. GaN is used in the near infrared light-emitting semiconductor element, and said near infrared light-emitting semiconductor element includes an active layer sandwiched between an n-type layer and a p-type layer on a substrate. An organometallic vapor phase growth method is used to add the active layer to the GaN in order to substitute Tm with Ga.

Two-dimensional, ordered, double transition metals carbides having a nominal unit cell composition M′2M″NXN+1

The present disclosure is directed to compositions comprising at least one layer having first and second surfaces, each layer comprising: a substantially two-dimensional array of crystal cells, each crystal cell having an empirical formula of M′.sub.2M″nX.sub.n+1, such that each X is positioned within an octahedral array of M′ and M″; wherein M′ and M″ each comprise different Group 11113, WE, VB, or VIB metals; each X is C, N, or a combination thereof; n=1 or 2; and wherein the M′ atoms are substantially present as two-dimensional outer arrays of atoms within the two-dimensional array of crystal cells; the M″ atoms are substantially present as two-dimensional inner arrays of atoms within the two-dimensional array of crystal cells; and the two dimensional inner arrays of M″ atoms are sandwiched between the two-dimensional outer arrays of M′ atoms within the two-dimensional army of crystal cells.

Two-dimensional, ordered, double transition metals carbides having a nominal unit cell composition M′2M″NXN+1

The present disclosure is directed to compositions comprising at least one layer having first and second surfaces, each layer comprising: a substantially two-dimensional array of crystal cells, each crystal cell having an empirical formula of M′.sub.2M″nX.sub.n+1, such that each X is positioned within an octahedral array of M′ and M″; wherein M′ and M″ each comprise different Group 11113, WE, VB, or VIB metals; each X is C, N, or a combination thereof; n=1 or 2; and wherein the M′ atoms are substantially present as two-dimensional outer arrays of atoms within the two-dimensional array of crystal cells; the M″ atoms are substantially present as two-dimensional inner arrays of atoms within the two-dimensional array of crystal cells; and the two dimensional inner arrays of M″ atoms are sandwiched between the two-dimensional outer arrays of M′ atoms within the two-dimensional army of crystal cells.

Methods of manufacturing engineered substrate structures for power and RF applications

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.

Methods of manufacturing engineered substrate structures for power and RF applications

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.