A single crystal CVD diamond component comprising: a surface, wherein at least a portion of said surface is formed of as-grown growth face single crystal CVD diamond material which has not been polished or etched and which has a surface roughness R.sub.a of no more than 100 nm; and a layer of NV.sup. defects, said layer of NV.sup. defects being disposed within 1 m of the surface, said layer of NV.sup. defects having a thickness of no more than 500 nm, and said layer of NV.sup. defects having a concentration of NV.sup. defects of at least 10.sup.5 NV.sup./cm.sup.2.

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-Al.sub.yGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-Al.sub.yGaN layer to the junction between the i-GaN channel layer and the i-Al.sub.xGaN layer.

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-Al.sub.yGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-Al.sub.yGaN layer to the junction between the i-GaN channel layer and the i-Al.sub.xGaN layer.

A synthetic diamond material comprises a surface, wherein the surface comprises a first surface region comprising a first concentration of quantum spin defects. A second surface region has a predetermined area and is located adjacent to the first surface region, the second region comprising a second concentration of quantum spin defects. The first concentration of quantum spin defects is at least ten times greater than the second concentration of quantum spin defects, and at least one of the first or second surface regions comprises chemical vapour deposition, CVD, synthetic diamond. A method of producing the synthetic diamond material is also disclosed.

There is described a method of manufacturing a substrate for an optoelectronic device. The method has the steps of: supporting a first layer of a first crystalline material on a second layer of a second crystalline material different from said first crystalline material thereby exposing crystalline defects at a surface of said first layer; etching said first layer using first etching conditions, at least some of said crystalline defects expanding into pores running from said surface of the first layer towards said second layer; and heating said first and second layers up to a first temperature for a first period of time within a given environment, said heating transforming said pores into nanovoids attracting at least some of said crystalline defects away from said surface. In some embodiments, the method has a step of reheating the layers or a step of forming a pore containing region within the first layer.

There is described a method of manufacturing a substrate for an optoelectronic device. The method has the steps of: supporting a first layer of a first crystalline material on a second layer of a second crystalline material different from said first crystalline material thereby exposing crystalline defects at a surface of said first layer; etching said first layer using first etching conditions, at least some of said crystalline defects expanding into pores running from said surface of the first layer towards said second layer; and heating said first and second layers up to a first temperature for a first period of time within a given environment, said heating transforming said pores into nanovoids attracting at least some of said crystalline defects away from said surface. In some embodiments, the method has a step of reheating the layers or a step of forming a pore containing region within the first layer.

A method for manufacturing a semiconductor device includes epitaxially growing a carrier-transport layer of a first conductivity type on a substrate of silicon carbide; irradiating the carrier-transport layer with a first light having a wavelength equal to or less than an absorption-edge wavelength of silicon carbide at a temperature of less than 400 degrees Celsius so as to expand a stacking fault originating from a basal plane dislocation which are propagated from the substrate to the carrier-transport layer; heating the carrier-transport layer in which the stacking fault has expanded so as to shrink the stacking fault, at a shrinking temperature of 400 degrees Celsius or more and 1000 degrees Celsius or less; and forming a carrier-injection region of a second conductivity type on the carrier-transport layer, the carrier-injection region injects carriers into the carrier-transport layer.

A method for manufacturing a semiconductor device includes epitaxially growing a carrier-transport layer of a first conductivity type on a substrate of silicon carbide; irradiating the carrier-transport layer with a first light having a wavelength equal to or less than an absorption-edge wavelength of silicon carbide at a temperature of less than 400 degrees Celsius so as to expand a stacking fault originating from a basal plane dislocation which are propagated from the substrate to the carrier-transport layer; heating the carrier-transport layer in which the stacking fault has expanded so as to shrink the stacking fault, at a shrinking temperature of 400 degrees Celsius or more and 1000 degrees Celsius or less; and forming a carrier-injection region of a second conductivity type on the carrier-transport layer, the carrier-injection region injects carriers into the carrier-transport layer.

A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 610.sup.17 cm.sup.3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.

A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 610.sup.17 cm.sup.3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 m. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.