Disclosed are a silicon carbide powder, a method of manufacturing a silicon carbide powder, and a silicon carbide wafer. More particularly, the silicon carbide powder includes carbon and silicon and in the silicon carbide powder, O1s/C1s of a surface measured by X-ray photoelectron spectroscopy is 0.28 or less.

Disclosed are a silicon carbide powder, a method of manufacturing a silicon carbide powder, and a silicon carbide wafer. More particularly, the silicon carbide powder includes carbon and silicon and in the silicon carbide powder, O1s/C1s of a surface measured by X-ray photoelectron spectroscopy is 0.28 or less.

A method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising: a) a step of providing a donor substrate made of monocrystalline silicon carbide, b) a step of ion implantation of light species into the donor substrate, to form a buried brittle plane delimiting the thin layer between the buried brittle plane and a free surface of the donor substrate, c) a succession of n steps of forming crystalline carrier layers, with n greater than or equal to 2; the n crystalline carrier layers being positioned on the front face of the donor substrate successively one on the other, and forming the carrier substrate; each formation step comprising: direct liquid injection chemical vapor deposition, at a temperature below 900° C., to form a carrier layer, the carrier layer being formed by an at least partially amorphous SiC matrix, and having a thickness of less than or equal to 200 microns; a crystallization heat treatment of the carrier layer, at a temperature of less than or equal to 1000° C., to form a crystalline carrier layer; d) a step of separation along the buried brittle plane, to form, on the one hand, a composite structure comprising the thin layer on the carrier substrate and, on the other hand, the rest of the donor substrate.

A method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising: a) a step of providing a donor substrate made of monocrystalline silicon carbide, b) a step of ion implantation of light species into the donor substrate, to form a buried brittle plane delimiting the thin layer between the buried brittle plane and a free surface of the donor substrate, c) a succession of n steps of forming crystalline carrier layers, with n greater than or equal to 2; the n crystalline carrier layers being positioned on the front face of the donor substrate successively one on the other, and forming the carrier substrate; each formation step comprising: direct liquid injection chemical vapor deposition, at a temperature below 900° C., to form a carrier layer, the carrier layer being formed by an at least partially amorphous SiC matrix, and having a thickness of less than or equal to 200 microns; a crystallization heat treatment of the carrier layer, at a temperature of less than or equal to 1000° C., to form a crystalline carrier layer; d) a step of separation along the buried brittle plane, to form, on the one hand, a composite structure comprising the thin layer on the carrier substrate and, on the other hand, the rest of the donor substrate.

The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

A silicon carbide substrate is composed of silicon carbide, and when a main surface thereof is etched with chlorine gas, the overall length of linear etch-pit groups observed in the main surface is equal to or less than the diameter of the substrate.

A silicon carbide substrate is composed of silicon carbide, and when a main surface thereof is etched with chlorine gas, the overall length of linear etch-pit groups observed in the main surface is equal to or less than the diameter of the substrate.

The invention concerns monocrystalline dislocation-free Ge, n-type doped, and having a resistivity of less than 10 mOhm.Math.cm, characterized in that phosphorus is the single dopant. Such crystals can be obtained by using the Czochralski pulling technique with GeP as dopant.

The invention concerns monocrystalline dislocation-free Ge, n-type doped, and having a resistivity of less than 10 mOhm.Math.cm, characterized in that phosphorus is the single dopant. Such crystals can be obtained by using the Czochralski pulling technique with GeP as dopant.